Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
NOTE
The INL errors, see Section 4.9.4, aren’t in the usable temperature range of the ADC.
4.9.6. List of Registers
The ADC registers start at a base address of 0x4004c000 (defined as ADC_BASE in SDK).
Table 577. List of ADC
registers
Offset Name Info
0x00 CS ADC Control and Status
0x04 RESULT Result of most recent ADC conversion
0x08 FCS FIFO control and status
0x0c FIFO Conversion result FIFO
0x10 DIV Clock divider. If non-zero, CS_START_MANY will start
conversions
at regular intervals rather than back-to-back.
The divider is reset when either of these fields are written.
Total period is 1 + INT + FRAC / 256
0x14 INTR Raw Interrupts
0x18 INTE Interrupt Enable
0x1c INTF Interrupt Force
0x20 INTS Interrupt status after masking & forcing
ADC: CS Register
Offset: 0x00
Description
ADC Control and Status
Table 578. CS Register
Bits Name Description Type Reset
31:21 Reserved. - - -
20:16 RROBIN Round-robin sampling. 1 bit per channel. Set all bits to 0 to
disable.
Otherwise, the ADC will cycle through each enabled
channel in a round-robin fashion.
The first channel to be sampled will be the one currently
indicated by AINSEL.
AINSEL will be updated after each conversion with the
newly-selected channel.
RW 0x00
15 Reserved. - - -
14:12 AINSEL Select analog mux input. Updated automatically in round-
robin mode.
RW 0x0
11 Reserved. - - -
10 ERR_STICKY Some past ADC conversion encountered an error. Write 1
to clear.
WC 0x0
RP2040 Datasheet
4.9. ADC and Temperature Sensor 585