Datasheet

Bits Name Description Type Reset
1 SHIFT If 1: FIFO results are right-shifted to be one byte in size.
Enables DMA to byte buffers.
RW 0x0
0 EN If 1: write result to the FIFO after each conversion. RW 0x0
ADC: FIFO Register
Offset: 0x0c
Description
Conversion result FIFO
Table 581. FIFO
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15 ERR 1 if this particular sample experienced a conversion error.
Remains in the same location if the sample is shifted.
RF -
14:12 Reserved. - - -
11:0 VAL RF -
ADC: DIV Register
Offset: 0x10
Description
Clock divider. If non-zero, CS_START_MANY will start conversions
at regular intervals rather than back-to-back.
The divider is reset when either of these fields are written.
Total period is 1 + INT + FRAC / 256
Table 582. DIV
Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:8 INT Integer part of clock divisor. RW 0x0000
7:0 FRAC Fractional part of clock divisor. First-order delta-sigma. RW 0x00
ADC: INTR Register
Offset: 0x14
Description
Raw Interrupts
Table 583. INTR
Register
Bits Name Description Type Reset
31:1 Reserved. - - -
0 FIFO Triggered when the sample FIFO reaches a certain level.
This level can be programmed via the FCS_THRESH field.
RO 0x0
ADC: INTE Register
Offset: 0x18
RP2040 Datasheet
4.9. ADC and Temperature Sensor 587