Datasheet

Table 73.
INTERP1_PEEK_FULL
Register
Bits Description Type Reset
31:0 Read FULL result, without altering any internal state (PEEK). RO 0x00000000
SIO: INTERP1_CTRL_LANE0 Register
Offset: 0x0ec
Description
Control register for lane 0
Table 74.
INTERP1_CTRL_LANE
0 Register
Bits Name Description Type Reset
31:26 Reserved. - - -
25 OVERF Set if either OVERF0 or OVERF1 is set. RO 0x0
24 OVERF1 Indicates if any masked-off MSBs in ACCUM1 are set. RO 0x0
23 OVERF0 Indicates if any masked-off MSBs in ACCUM0 are set. RO 0x0
22 CLAMP Only present on INTERP1 on each core. If CLAMP mode is
enabled:
- LANE0 result is shifted and masked ACCUM0, clamped
by a lower bound of
BASE0 and an upper bound of BASE1.
- Signedness of these comparisons is determined by
LANE0_CTRL_SIGNED
RW 0x0
21 Reserved. - - -
20:19 FORCE_MSB ORed into bits 29:28 of the lane result presented to the
processor on the bus.
No effect on the internal 32-bit datapath. Handy for using
a lane to generate sequence
of pointers into flash or SRAM.
RW 0x0
18 ADD_RAW If 1, mask + shift is bypassed for LANE0 result. This does
not affect FULL result.
RW 0x0
17 CROSS_RESULT If 1, feed the opposite lane’s result into this lane’s
accumulator on POP.
RW 0x0
16 CROSS_INPUT If 1, feed the opposite lane’s accumulator into this lane’s
shift + mask hardware.
Takes effect even if ADD_RAW is set (the CROSS_INPUT
mux is before the shift+mask bypass)
RW 0x0
15 SIGNED If SIGNED is set, the shifted and masked accumulator
value is sign-extended to 32 bits
before adding to BASE0, and LANE0 PEEK/POP appear
extended to 32 bits when read by processor.
RW 0x0
14:10 MASK_MSB The most-significant bit allowed to pass by the mask
(inclusive)
Setting MSB < LSB may cause chip to turn inside-out
RW 0x00
9:5 MASK_LSB The least-significant bit allowed to pass by the mask
(inclusive)
RW 0x00
4:0 SHIFT Logical right-shift applied to accumulator before masking RW 0x00
SIO: INTERP1_CTRL_LANE1 Register
RP2040 Datasheet
2.3. Processor subsystem 58