Datasheet

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National Semiconductor Microwire
On RP2040, the DW_apb_ssi is a component of the flash execute-in-place subsystem (see Section 2.6.3), and provides
communication with an external SPI, dual-SPI or quad-SPI flash device.
4.10.2.1. IO connections
The SSI controller connects to the following pins:
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QSPI_SCLK Connected to output clock sclk_out
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QSPI_SS_N Connected to chip select ss_o_n
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QSPI_SD[3:0] Connected to data bus txd and rxd
Some pins on the IP are tied off as not used:
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ss_in_n is tied high
Clock connections are as follows:
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pclk and sclk are driven from clk_sys
4.10.3. IP Modifications
The following modifications were made to the Synopsys DW_apb_ssi hardware:
1. XIP accesses are byte-swapped, such that the least-addressed byte is in the least-significant position
2. When SPI_CTRLR0_INST_L is 0, the XIP instruction field is appended to the end of the address for XIP accesses,
rather than prepended to the beginning
3.
The reset value of DMARDLR is increased from 0 to 4. The SSI to DMA handshaking on RP2040 requests only single
transfers or bursts of four, depending on whether the RX FIFO level has reached DMARDLR, so DMARDLR should not be
changed from this value.
The first of these changes allows mixed-size accesses by a little-endian busmaster, such as the RP2040 DMA, or the
Cortex-M0+ configuration used on RP2040. Note that this only applies to XIP accesses (RP2040 system addresses in
the range 0x10000000 to 0x13ffffff), not to direct access to the DW_apb_ssi FIFOs. When accessing the SSI directly, it
may be necessary for software to swap bytes manually, or to use the RP2040 DMA’s byte swap feature.
The second supports issuing of continuation bits following the XIP address, so that command-prefix-free XIP modes
can be supported (e.g. EBh Quad I/O Fast Read on Winbond devices), for greater performance. For example, the
following configuration would be used to issue a standard 03h serial read command for each access to the XIP address
window:
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SPI_CTRLR0_INST_L = 8 bits
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SPI_CTRLR0_ADDR_L = 24 bits
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SPI_CTRLR0_XIP_CMD = 0x03
This will first issue eight command bits (0x03), then issue 24 address bits, then clock in the data bits. The configuration
used for EBh quad read, after the flash has entered the XIP state, would be:
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SPI_CTRLR0_INST_L = 0
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SPI_CTRLR0_ADDR_L = 32 bits
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SPI_CTRLR0_XIP_CMD = 0xa0 (continuation code on W25Qx devices)
For each XIP access, the DW_apb_ssi will issue 32 "address" bits, consisting of the 24 LSBs of the RP2040 system bus
address, followed by the 8-bit continuation code 0xa0. No command prefix is issued.
RP2040 Datasheet
4.10. SSI 590