Datasheet

Transmit FIFO Overflow Interrupt (ssi_txo_intr)
Set when an APB access attempts to write into the transmit FIFO after it has been completely filled. When set, data
written from the APB is discarded. This interrupt remains set until you read the transmit FIFO overflow interrupt
clear register (TXOICR).
Receive FIFO Full Interrupt (ssi_rxf_intr)
Set when the receive FIFO is equal to or above its threshold value plus 1 and requires service to prevent an
overflow. The threshold value, set through a software-programmable register, determines the level of receive FIFO
entries at which an interrupt is generated. This interrupt is cleared by hardware when data are read from the receive
FIFO buffer, bringing it below the threshold level.
Receive FIFO Overflow Interrupt (ssi_rxo_intr)
Set when the receive logic attempts to place data into the receive FIFO after it has been completely filled. When set,
newly received data are discarded. This interrupt remains set until you read the receive FIFO overflow interrupt clear
register (RXOICR).
Receive FIFO Underflow Interrupt (ssi_rxu_intr)
Set when an APB access attempts to read from the receive FIFO when it is empty. When set, 0s are read back from
the receive FIFO. This interrupt remains set until you read the receive FIFO underflow interrupt clear register
(RXUICR).
Multi-Master Contention Interrupt (ssi_mst_intr)
Present only when the DW_apb_ssi component is configured as a serial-master device. The interrupt is set when
another serial master on the serial bus selects the DW_apb_ssi master as a serial-slave device and is actively
transferring data. This informs the processor of possible contention on the serial bus. This interrupt remains set
until you read the multi-master interrupt clear register (MSTICR).
Combined Interrupt Request (ssi_intr)
OR’ed result of all the above interrupt requests after masking. To mask this interrupt signal, you must mask all other
DW_apb_ssi interrupt requests.
4.10.8. Transfer Modes
When transferring data on the serial bus, the DW_apb_ssi operates in the modes discussed in this section. The transfer
mode (TMOD) is set by writing to control register 0 (CTRLR0).
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NOTE
The transfer mode setting does not affect the duplex of the serial transfer. TMOD is ignored for Microwire transfers,
which are controlled by the MWCR register.
4.10.8.1. Transmit and Receive
When TMOD = 00b, both transmit and receive logic are valid. The data transfer occurs as normal according to the
selected frame format (serial protocol). Transmit data are popped from the transmit FIFO and sent through the txd line
to the target device, which replies with data on the rxd line. The receive data from the target device is moved from the
receive shift register into the receive FIFO at the end of each data frame.
4.10.8.2. Transmit Only
When TMOD = 01b, the receive data are invalid and should not be stored in the receive FIFO. The data transfer occurs as
normal, according to the selected frame format (serial protocol). Transmit data are popped from the transmit FIFO and
sent through the txd line to the target device, which replies with data on the rxd line. At the end of the data frame, the
receive shift register does not load its newly received data into the receive FIFO. The data in the receive shift register is
overwritten by the next transfer. You should mask interrupts originating from the receive logic when this mode is
RP2040 Datasheet
4.10. SSI 594