Datasheet

that the setup times on the rxd signal are within range; this results in reducing the frequency of the serial interface.
When the RXD Sample Delay logic is included, the user can dynamically program a delay value in order to move the
sampling time of the rxd signal equal to a number of ssi_clk cycles from the default.
The sample delay logic has a resolution of one ssi_clk cycle. Software can “train” the serial bus by coding a loop that
continually reads from the slave and increments the master’s RXD Sample Delay value until the correct data is received
by the master.
4.10.9.1.2. Data Transfers
Data transfers are started by the serial-master device. When the DW_apb_ssi is enabled (SSI_EN=1), at least one valid
data entry is present in the transmit FIFO and a serial-slave device is selected. When actively transferring data, the busy
flag (BUSY) in the status register (SR) is set. You must wait until the busy flag is cleared before attempting a new serial
transfer.

NOTE
The BUSY status is not set when the data are written into the transmit FIFO. This bit gets set only when the target
slave has been selected and the transfer is underway. After writing data into the transmit FIFO, the shift logic does
not begin the serial transfer until a positive edge of the sclk_out signal is present. The delay in waiting for this
positive edge depends on the baud rate of the serial transfer. Before polling the BUSY status, you should first poll the
TFE status (waiting for 1) or wait for BAUDR * ssi_clk clock cycles.
4.10.9.1.3. Master SPI and SSP Serial Transfers
When the transfer mode is “transmit and receive” or “transmit only” (TMOD = 00b or TMOD = 01b, respectively), transfers
are terminated by the shift control logic when the transmit FIFO is empty. For continuous data transfers, you must
ensure that the transmit FIFO buffer does not become empty before all the data have been transmitted. The transmit
FIFO threshold level (TXFTLR) can be used to early interrupt (ssi_txe_intr) the processor indicating that the transmit
FIFO buffer is nearly empty. When a DMA is used for APB accesses, the transmit data level (DMATDLR) can be used to
early request (dma_tx_req) the DMA Controller, indicating that the transmit FIFO is nearly empty. The FIFO can then be
refilled with data to continue the serial transfer. The user may also write a block of data (at least two FIFO entries) into
the transmit FIFO before enabling a serial slave. This ensures that serial transmission does not begin until the number
of data-frames that make up the continuous transfer are present in the transmit FIFO.
When the transfer mode is “receive only” (TMOD = 10b), a serial transfer is started by writing one “dummy” data word
into the transmit FIFO when a serial slave is selected. The txd output from the DW_apb_ssi is held at a constant logic
level for the duration of the serial transfer. The transmit FIFO is popped only once at the beginning and may remain
empty for the duration of the serial transfer. The end of the serial transfer is controlled by the “number of data frames”
(NDF) field in control register 1 (CTRLR1).
If, for example, you want to receive 24 data frames from a serial-slave peripheral, you should program the NDF field with
the value 23; the receive logic terminates the serial transfer when the number of frames received is equal to the NDF
value + 1. This transfer mode increases the bandwidth of the APB bus as the transmit FIFO never needs to be serviced
during the transfer. The receive FIFO buffer should be read each time the receive FIFO generates a FIFO full interrupt
request to prevent an overflow.
When the transfer mode is “eeprom_read” (TMOD = 11b), a serial transfer is started by writing the opcode and/or
address into the transmit FIFO when a serial slave (EEPROM) is selected. The opcode and address are transmitted to
the EEPROM device, after which read data is received from the EEPROM device and stored in the receive FIFO. The end
of the serial transfer is controlled by the NDF field in the control register 1 (CTRLR1).
RP2040 Datasheet
4.10. SSI 597