Datasheet

Offset: 0x0f0
Description
Control register for lane 1
Table 75.
INTERP1_CTRL_LANE
1 Register
Bits Name Description Type Reset
31:21 Reserved. - - -
20:19 FORCE_MSB ORed into bits 29:28 of the lane result presented to the
processor on the bus.
No effect on the internal 32-bit datapath. Handy for using
a lane to generate sequence
of pointers into flash or SRAM.
RW 0x0
18 ADD_RAW If 1, mask + shift is bypassed for LANE1 result. This does
not affect FULL result.
RW 0x0
17 CROSS_RESULT If 1, feed the opposite lane’s result into this lane’s
accumulator on POP.
RW 0x0
16 CROSS_INPUT If 1, feed the opposite lane’s accumulator into this lane’s
shift + mask hardware.
Takes effect even if ADD_RAW is set (the CROSS_INPUT
mux is before the shift+mask bypass)
RW 0x0
15 SIGNED If SIGNED is set, the shifted and masked accumulator
value is sign-extended to 32 bits
before adding to BASE1, and LANE1 PEEK/POP appear
extended to 32 bits when read by processor.
RW 0x0
14:10 MASK_MSB The most-significant bit allowed to pass by the mask
(inclusive)
Setting MSB < LSB may cause chip to turn inside-out
RW 0x00
9:5 MASK_LSB The least-significant bit allowed to pass by the mask
(inclusive)
RW 0x00
4:0 SHIFT Logical right-shift applied to accumulator before masking RW 0x00
SIO: INTERP1_ACCUM0_ADD Register
Offset: 0x0f4
Table 76.
INTERP1_ACCUM0_AD
D Register
Bits Description Type Reset
31:24 Reserved. - -
23:0 Values written here are atomically added to ACCUM0
Reading yields lane 0’s raw shift and mask value (BASE0 not added).
RW 0x000000
SIO: INTERP1_ACCUM1_ADD Register
Offset: 0x0f8
RP2040 Datasheet
2.3. Processor subsystem 59