Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
The direction of the data word is controlled by the MDD bit field (bit 1) in the Microwire Control Register (MWCR). When
MDD=0, this indicates that the DW_apb_ssi serial master receives data from the external serial slave. One clock cycle
after the LSB of the control word is transmitted, the slave peripheral responds with a dummy 0 bit, followed by the data
frame, which can be four to 32 bits in length. Data are propagated on the falling edge of the serial clock and captured on
the rising edge.
The slave-select signal is held active-low during the transfer and is de-asserted one-half clock cycle later, after the data
are transferred. Figure 134 shows the timing diagram for a single DW_apb_ssi serial master read from an external serial
slave.
sclk_out
txd
rxd
ss_0_n
ssi_oe_n
MSB LSB
Control word
LSB0 MSB
4 -32 bits
Figure 134. Single
DW_apb_ssi Master
Microwire Serial
Transfer (MDD=0)
Figure 135 shows how the data and control frames are structured in the transmit FIFO prior to the transfer; the value
programmed into the MWCR register is also shown.
Tx FIFO Buffer
FIFO Status Prior to
Transfer
FIFO Status on
Completion of Transfer
Rx FIFO Buffer
Location n
Location 3
Location 2
Location 1
Location 0
Location n
Location 3
Location 2
Location 1
Location 0
Write DR
NULL
NULL SHIFT LOGIC
NULL
NULL
Ctrl Word(0)
Rx FIFO Empty
rxd
txd
NULL
NULL
NULL
Rx_Data(0)
NULL
Tx FIFO Empty
Read DR
0
MWHS
MWCR
0
MDD
0
MWMOD
Figure 135. FIFO
Status for Single
Microwire Transfer
(receiving data frame)
Continuous transfers for the Microwire protocol can be sequential or nonsequential, and are controlled by the MWMOD
bit field (bit 0) in the MWCR register.
Nonsequential continuous transfers occur as illustrated in Figure 136, with the control word for the next transfer
following immediately after the LSB of the current data word.
sclk_out
txd
rxd
ss_0_n
ssi_oe_n
MSB LSB
Control word 0
MSB LSB
LSB0 MSB
Control word 1
Data Word 0 Data Word 1
LSB0 MSB
Figure 136.
Continuous
Nonsequential
Microwire Transfer
(receiving data frame)
The only modification needed to perform a continuous nonsequential transfer is to write more control words into the
transmit FIFO buffer; this is illustrated in Figure 137. In this example, two data words are read from the external serial-
slave device.
RP2040 Datasheet
4.10. SSI 605