Datasheet

Table 77.
INTERP1_ACCUM1_AD
D Register
Bits Description Type Reset
31:24 Reserved. - -
23:0 Values written here are atomically added to ACCUM1
Reading yields lane 1’s raw shift and mask value (BASE1 not added).
RW 0x000000
SIO: INTERP1_BASE_1AND0 Register
Offset: 0x0fc
Table 78.
INTERP1_BASE_1AND
0 Register
Bits Description Type Reset
31:0 On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
WO 0x00000000
SIO: SPINLOCK0, SPINLOCK1, …, SPINLOCK30, SPINLOCK31 Registers
Offsets: 0x100, 0x104, …, 0x178, 0x17c
Table 79. SPINLOCK0,
SPINLOCK1, …,
SPINLOCK30,
SPINLOCK31
Registers
Bits Description Type Reset
31:0 Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
wins.
The value returned on success is 0x1 << lock number.
RO 0x00000000
2.3.2. Interrupts
Each core is equipped with a standard ARM Nested Vectored Interrupt Controller (NVIC) which has 32 interrupt inputs.
Each NVIC has the same interrupts routed to it, with the exception of the GPIO interrupts: there is one GPIO interrupt per
bank, per core. These are completely independent, so e.g. core 0 can be interrupted by GPIO 0 in bank 0, and core 1 by
GPIO 1 in the same bank.
On RP2040, only the lower 26 IRQ signals are connected on the NVIC, and IRQs 26 to 31 are tied to zero (never firing).
The core can still be forced to enter the relevant interrupt handler by writing bits 26 to 31 in the NVIC ISPR register.
Table 80. Interrupts
IRQ Interrupt Source IRQ Interrupt Source IRQ Interrupt Source IRQ Interrupt Source IRQ Interrupt Source
0
TIMER_IRQ_0
6
XIP_IRQ
12
DMA_IRQ_1
18
SPI0_IRQ
24
I2C1_IRQ
1
TIMER_IRQ_1
7
PIO0_IRQ_0
13
IO_IRQ_BANK0
19
SPI1_IRQ
25
RTC_IRQ
2
TIMER_IRQ_2
8
PIO0_IRQ_1
14
IO_IRQ_QSPI
20
UART0_IRQ
3
TIMER_IRQ_3
9
PIO1_IRQ_0
15
SIO_IRQ_PROC0
21
UART1_IRQ
4
PWM_IRQ_WRAP
10
PIO1_IRQ_1
16
SIO_IRQ_PROC1
22
ADC_IRQ_FIFO
5
USBCTRL_IRQ
11
DMA_IRQ_0
17
CLOCKS_IRQ
23
I2C0_IRQ
Nested interrupts are supported in hardware: a lower-priority interrupt can be preempted by a higher-priority interrupt (or
another exception e.g. HardFault), and the lower-priority interrupt will resume once higher-priority exceptions have
completed. The priority order is determined by:
•
First, the dynamic priority level configured per interrupt by the NVIC_IPR0-7 registers. The Cortex-M0+ implements
the two most significant bits of an 8-bit priority field, so four priority levels are available, and the numerically-lowest
RP2040 Datasheet
2.3. Processor subsystem 60