Datasheet

sclk_out
txd
rxd
ss_0_n
ssi_oe_n
MSB LSB
Start Bit
Busy Ready
Control Word 0
Figure 146. Microwire
Control Word
4.10.10.4. Enhanced SPI Modes
DW_apb_ssi supports the dual and quad modes of SPI in RP2040; octal mode is not supported. txd, rxd and ssi_oe_n
signals are four bits wide.
Data is shifted out/in on more than one line, increasing the overall throughput. All four combinations of the serial clock’s
polarity and phase are valid in this mode and work the same as in normal SPI mode. Dual SPI, or Quad SPI modes
function similarly except for the width of txd, rxd and ssi_oe_n signals. The mode of operation (write/read) can be
selected using the CTRLR0.TMOD field.
4.10.10.4.1. Write Operation in Enhanced SPI Modes
Dual, or Quad, SPI write operations can be divided into three parts:
•
Instruction phase
•
Address phase
•
Data phase
The following register fields are used for a write operation:
•
CTRLR0.SPI_FRF - Specifies the format in which the transmission happens for the frame.
•
SPI_CTRLR0 (Control Register 0 register) – Specifies length of instruction, address, and data.
•
SPI_CTRLR0.INST_L – Specifies length of an instruction (possible values for an instruction are 0, 4, 8, or 16 bits.)
•
SPI_CTRLR0.ADDR_L – Specifies address length (See Table 589 for decode values)
•
CTRLR0.DFS or CTRLR0.DFS_32 – Specifies data length.
An instruction takes one FIFO location. An address can take more than one FIFO locations.
Both the instruction and address must be programmed in the data register (DR). DW_apb_ssi will wait until both have
been programmed to start the write operation.
The instruction, address and data can be programmed to send in dual/quad mode, which can be selected from the
SPI_CTRLR0.TRANS_TYPE and CTRLR0.SPI_FRF fields.

NOTE
•
If CTRLR0.SPI_FRF is selected to be "Standard SPI Format", everything is sent in Standard SPI mode and
SPI_CTRLR0.TRANS_TYPE field is ignored.
•
CTRLR0.SPI_FRF is only applicable if CTRLR0.FRF is programmed to 00b.
Figure 147 shows a typical write operation in Dual, or Quad, SPI Mode. The value of N will be: 7 if SSI_SPI_MODE is set
to 3, 3 if SSI_SPI_MODE is set to 2, and 1 if SSI_SPI_MODE is set to 1. For 1-write operation, the instruction and address
are sent only once followed by data frames programmed in DR until the transmit FIFO becomes empty.
RP2040 Datasheet
4.10. SSI 609