Datasheet

4.10.10.4.2. Read Operation in Enhanced SPI Modes
A Dual, or Quad, SPI read operation can be divided into four phases:
•
Instruction phase
•
Address phase
•
Wait cycles
•
Data phase
Wait Cycles can be programmed using SPI_CTRLR0.WAIT_CYCLES field. The value programmed into
SPI_CTRLR0.WAIT_CYCLES is mapped directly to sclk_out times. For example, WAIT_CYCLES=0 indicates no Wait,
WAIT_CYCLES=1, indicates one wait cycle and so on. The wait cycles are introduced for target slave to change their
mode from input to output and the wait cycles can vary for different devices.
For a READ operation, DW_apb_ssi sends instruction and control data once and waits until it receives NDF (CTRLR1
register) number of data frames and then de-asserts slave select signal.
Figure 152 shows a typical read operation in dual quad SPI mode. The value of N will be: 3 if SSI_SPI_MODE is set to
Quad mode, and 1 if SSI_SPI_MODE is set to Dual mode.
sclk_out
txd[N:0]
ss_oe_n[N:0]
ss_oe_n
rxd[N:0]
INSTRUCTION ADDRESS WAIT CYCLES
DATA
Figure 152. Typical
Read Operation in
Enhanced SPI Mode
To initiate a dual/quad read operation, CTRLR0.SPI_FRF must be set to 01/10/11 respectively. This will set the transfer
type, now for each read command data will be transferred in the format specified in CTLR0.SPI_FRF field.
Following are the possible cases of write operation in enhanced SPI modes:
Case A: Instruction and address both transmitted in standard SPI format
For this, SPI_CTRLR0.TRANS_TYPE field should be set to 00b. Figure 153 shows the timing diagram when both
instruction and address are transferred in standard SPI format. The figure also shows WAIT cycles after address,
which can be programmed in the SPI_CTRLR0.WAIT_CYCLES field. The value of N will be 7 if CTRLR0.SPI_FRF is set
to 11b, 3 if CTRLR0.SPI_FRF is set to 10b, and 1 if CTRLR0.SPI_FRF is set to 01b.
sclk_out
txd[0]
txd[N-1:0]
rxd[N:0]
ssi_oe_n[0]
ssi_oe_n[N-1:0]
ss_0_n
INSTRUCTION ADDRESS WAIT CYCLES
DATA
Figure 153. Instruction
and Address
Transmitted in
Standard SPI Format
Case B: Instruction transmitted in standard and address transmitted in dual SPI format
For this, SPI_CTRLR0.TRANS_TYPE field should be set to 01b. Figure 154 shows the timing diagram in which
instruction is transmitted in standard format and address is transmitted in dual SPI format. The value of N will be 7
if CTRLR0.SPI_FRF is set to 11b, 3 if CTRLR0.SPI_FRF is set to 10b, and 1 if CTRLR0.SPI_FRF is set to 01b.
sclk_out
txd[0]
rxd[N:0]
txd[N-1:0]
ssi_oe_n[0]
ssi_oe_n[N-1:0]
ss_0_n
INSTRUCTION ADDRESS
ADDRESS
DATA
Figure 154. Instruction
Transmitted in
Standard and Address
Transmitted in
Enhanced SPI Format
RP2040 Datasheet
4.10. SSI 611