Datasheet

Case C: Instruction and Address both transmitted in Dual SPI format
For this, SPI_CTRLR0.TRANS_TYPE field must be set to 10b. Figure 155 shows the timing diagram in which both
instruction and address are transmitted in dual SPI format. The value of N will be: 7 if CTRLR0.SPI_FRF is set to 11b,
3 if CTRLR0.SPI_FRF is set to 10b, and 1 if CTRLR0.SPI_FRF is set to 01b.
sclk_out
txd[N:0]
rxd[N:0]
ssi_oe_n[N:0]
ss_0_n
INSTRUCTION ADDRESS
DATA
Figure 155. Instruction
and Address
Transmitted in
Enhanced SPI Format
Case D: No Instruction, No Address READ transfer
For this, SPI_CTRLR0.ADDR_L and SPI_CTRLR0.INST_L must be set to 0 and SPI_CTRLR0.WAIT_CYCLES must be
set to a non-zero value. Table 589 lists the ADDR_L decode value and the respective description for enhanced
(Dual/Quad) SPI modes.
Table 589. ADDR_L
Decode in Enhanced
SPI Mode
ADDR_L
Decode Value
Description
0000 0-bit Address Width
0001 4-bit Address Width
0010 8-bit Address Width
0011 12-bit Address Width
0100 16-bit Address Width
0101 20-bit Address Width
0110 24-bit Address Width
0111 28-bit Address Width
1000 32-bit Address Width
1001 36-bit Address Width
1010 40-bit Address Width
1011 44-bit Address Width
1100 48-bit Address Width
1101 52-bit Address Width
1110 56-bit Address Width
1111 60-bit Address Width
Figure 156 shows the timing diagram for such type of transfer. The value of N will be: 7 if CTRLR0.SPI_FRF is set to 11b,
3 if CTRLR0.SPI_FRF is set to 10b, and 1 if CTRLR0.SPI_FRF is set to 01b. To initiate this transfer, the software has to
perform a dummy write in the data register (DR), DW_apb_ssi will wait for programmed wait cycles and then fetch the
amount of data specified in NDF field.
sclk_out
txd[N:0]
rxd[N:0]
ssi_oe_n[N:0]
ss_0_n
WAIT CYCLES
DATA
Figure 156. No
Instruction and No
Address READ
Transfer
RP2040 Datasheet
4.10. SSI 612