Datasheet

sclk_out
ss_oe_n
rxd[N:0]
ss_oe_n[N:0]
txd[N:0]
D0
INST = Instruction Phase
A3, A2, A1, A0 = Address Bytes
D3, D2, D1, D0 = Data Bytes
A3 A2 A1 A0 D3 D2 D1
INST
Figure 158. DDR
Transfer with SCPH=0
and SCPOL=0
Figure 159 describes a DDR write transfer where instruction, address and data all are transferred in DDR format.
sclk_out
ss_0_n
rxd[N:0]
ssi_oe_n[N:0]
txd[N:0]
D0
INST-1, INST-2 = Instruction Bytes
A3, A2, A1, A0 = Address Bytes
D3, D2, D1, D0 = Data Bytes
A3 A2 A1 A0 D3 D2 D1
INST-1 INST-2
Figure 159. DDR
Transfer with
Instruction, Address
and Data Transmitted
in DDR Format

NOTE
In the DDR transfer, address and instruction cannot be programmed to a value of 0.
4.10.10.5.1. Transmitting Data in DDR Mode
In DDR mode, data is transmitted on both edges so that it is difficult to sample data correctly. DW_apb_ssi uses an
internal register to determine the edge on which the data should be transmitted. This will ensure that the receiver is able
to get a stable data while sampling. The internal register (DDR_DRIVE_EDGE) determines the edge on which the data is
transmitted. DW_apb_ssi sends data with respect to baud clock, which is an integral multiple of the internal clock
(ssi_clk * BAUDR). The data needs to be transmitted within half clock cycle (BAUDR/2), therefore the maximum value
for DDR_DRIVE_EDGE is equal to [(BAUDR/2)-1]. If the programmed value of DDR_DRIVE_EDGE is 0 then data is
transmitted edge-aligned with respect to sclk_out (baud clock). If the programmed value of DDR_DRIVE_EDGE is one
then the data is transmitted one ssi_clk before the edge of sclk_out.

NOTE
If the baud rate is programmed to be two, then the data will always be edge aligned.
Figure 160, Figure 161, and Figure 162 show examples of how data is transmitted using different values of the
DDR_DRIVE_EDGE register. The green arrows in these examples represent the points where data is driven. Baud rate
used in all these examples is 12. In Figure 160, transmit edge and driving edge of the data are the same. This is default
behavior in DDR mode.
sclk_out
ss_0_n
rxd[N:0]
ssi_oe_n[N:0]
ssi_clk
txd[N:0]
D0
INST = Instruction Phase
A3, A2, A1, A0 = Address Bytes
D3, D2, D1, D0 = Data Bytes
A3INST A2 A1 A0 D3 D2 D1
Figure 160. Transmit
Data With
DDR_DRIVE_EDGE = 0
Figure 160 shows the default behavior in which the transmit and driving edge of the data is the same.
RP2040 Datasheet
4.10. SSI 614