Datasheet

12 Data Items
12 Data Items
4 Data Items4 Data Items 4 Data Items
DMA
Multi-block Transfer
Level
DMA
Block
Level
DMA Burst
Transaction 2
DMA Burst
Transaction 1
DMA Burst
Transaction 3
Figure 164.
Breakdown of DMA
Transfer into Burst
Transactions. Block
size,
DMA.CTLx.BLOCKS
_TS = 12. Number of
data items per source
burst transaction,
DMA.CTLx.SRC_MS
IZE = 4. SSI receive
FIFO watermark level,
SSI.DMARDLR + 1 =
DMA.CTLx.SRC_MS
IZE = 4
If the DW_apb_ssi makes a transmit request to this channel, four data items are written to the DW_apb_ssi transmit
FIFO. Similarly, if the DW_apb_ssi makes a receive request to this channel, four data items are read from the
DW_apb_ssi receive FIFO. Three separate requests must be made to this DMA channel before all 12 data items are
written or read.
When the block size programmed into the DMA Controller is not a multiple of the burst transaction length, as shown in
Figure 165, a series of burst transactions followed by single transactions are needed to complete the block transfer.
15 Data Items
15 Data Items
4 Data Items
DMA
Multi-block Transfer
Level
DMA
Block
Level
DMA Burst
Transaction 1
4 Data Items
DMA Burst
Transaction 2
4 Data Items
DMA Burst
Transaction 3
1 Data Items
DMA Single
Transaction 1
1 Data Items
DMA Single
Transaction 2
1 Data Items
DMA Single
Transaction 3
Figure 165.
Breakdown of DMA
Transfer into Single
and Burst
Transactions. Block
size,
DMA.CTLx.BLOCK_
TS = 15. Number of
data items per burst
transaction,
DMA.CTLx.DEST_M
SIZE = 4. SSI
transmit FIFO
watermark level,
SSI.DMATDLR =
DMA.CTLx.DEST_M
SIZE = 4
4.10.12. APB Interface
The host processor accesses data, control, and status information on the DW_apb_ssi through the APB interface. APB
accesses to the DW_apb_ssi peripheral are described in the following subsections.
4.10.12.1. Control and Status Register APB Access
Control and status registers within the DW_apb_ssi are byte-addressable. The maximum width of the control or status
register in the DW_apb_ssi is 16 bits. Therefore all read and write operations to the DW_apb_ssi control and status
registers require only one APB access.
4.10.12.2. Data Register APB Access
The data register (DR) within the DW_apb_ssi is 32 bits wide in order to remain consistent with the maximum serial
transfer size (data frame). An APB write operation to DR moves data from pwdata into the transmit FIFO buffer. An APB
RP2040 Datasheet
4.10. SSI 618