Datasheet

level (level 0) is the highest priority.
•
Second, for interrupts with the same dynamic priority level, the lower-numbered IRQ has higher priority (using the
IRQ numbers given in the table above).
Some care has gone into arranging the RP2040 interrupt table to give a sensible default priority ordering, but individual
interrupts can be raised or lowered in priority, using NVIC_IPR0 through NVIC_IPR7, to suit a particular use case.
The 26 system IRQ signals are masked (NMI mask) and then ORed together creating the NMI signal for the core. The
NMI mask for each core can be configured using PROC0_NMI_MASK and PROC1_NMI_MASK in the Syscfg register
block. Each of these registers has one bit for each system interrupt, and the each core’s NMI is asserted if a system
interrupt is asserted and the corresponding NMI mask bit is set for that core.

CAUTION
If the watchdog is armed, and some bits are set on the core 1 NMI mask, the RESETS block (and hence Syscfg)
should be included in the watchdog reset list. Otherwise, following a watchdog event, core 1 NMI may be asserted
when the core enter the bootrom. It is safe for core 0 to take an NMI when entering the bootrom (the handler will
clear the NMI mask).
2.3.3. Event Signals
The Cortex-M0+ can enter a sleep state until an "event" (or interrupt) takes place, using the WFE instruction. It can also
generate events, using the SEV instruction. On RP2040 the event signals are cross-wired between the two processors, so
that an event sent by one processor will be received on the other.

NOTE
the event flag is "sticky", so if both processors send an event (SEV) simultaneously, and then both go to sleep (WFE),
they will both wake immediately, rather than getting stuck in a sleep state.
While in a WFE (or WFI) sleep state, the processor can shut off its internal clock gates, consuming much less power. When
both processors are sleeping, and the DMA is inactive, RP2040 as a whole can enter a sleep state, disabling clocks on
unused infrastructure such as the busfabric, and waking automatically when one of the processors wakes. See Section
2.11.2.
2.3.4. Debug
The 2-wire Serial Wire Debug (SWD) port provides access to hardware and software debug features including:
•
Loading firmware into SRAM or external flash memory
•
Control of processor execution: run/halt, step, set breakpoints, other standard Arm debug functionality
•
Access to processor architectural state
•
Access to memory and memory-mapped IO via the system bus
The SWD bus is exposed on two dedicated pins and is immediately available after power-on.
Debug access is via independent DAPs (one per core) attached to a shared multidrop SWD bus (SWD v2). Each DAP will
only respond to debug commands if correctly addressed by a SWD TARGETSEL command; all others tristate their outputs.
Additionally, a Rescue DP (see Section 2.3.4.2) is available which is connected to system control features. Default
addresses of each debug port are given below:
•
Core 0: 0x01002927
•
Core 1: 0x11002927
•
Rescue DP: 0xf1002927
RP2040 Datasheet
2.3. Processor subsystem 61