Datasheet

read operation from DR moves data from the receive FIFO buffer onto prdata.
The DW_apb_ssi DR can be written/read in one APB access.

NOTE
The DR register in the DW_apb_ssi occupies sixty-four 32-bit locations of the memory map to facilitate AHB burst
transfers. There are no burst transactions on the APB bus itself, but DW_apb_ssi supports the AHB bursts that
happen on the AHB side of the AHB/APB bridge. Writing to any of these address locations has the same effect as
pushing the data from the pwdata bus into the transmit FIFO. Reading from any of these locations has the same
effect as popping data from the receive FIFO onto the prdata bus. The FIFO buffers on the DW_apb_ssi are not
addressable.
4.10.13. List of Registers
The SSI registers start at a base address of 0x18000000 (defined as XIP_SSI_BASE in SDK).
Table 592. List of SSI
registers
Offset Name Info
0x00 CTRLR0 Control register 0
0x04 CTRLR1 Master Control register 1
0x08 SSIENR SSI Enable
0x0c MWCR Microwire Control
0x10 SER Slave enable
0x14 BAUDR Baud rate
0x18 TXFTLR TX FIFO threshold level
0x1c RXFTLR RX FIFO threshold level
0x20 TXFLR TX FIFO level
0x24 RXFLR RX FIFO level
0x28 SR Status register
0x2c IMR Interrupt mask
0x30 ISR Interrupt status
0x34 RISR Raw interrupt status
0x38 TXOICR TX FIFO overflow interrupt clear
0x3c RXOICR RX FIFO overflow interrupt clear
0x40 RXUICR RX FIFO underflow interrupt clear
0x44 MSTICR Multi-master interrupt clear
0x48 ICR Interrupt clear
0x4c DMACR DMA control
0x50 DMATDLR DMA TX data level
0x54 DMARDLR DMA RX data level
0x58 IDR Identification register
0x5c SSI_VERSION_ID Version ID
RP2040 Datasheet
4.10. SSI 619