Datasheet

Offset Name Info
0x60 DR0 Data Register 0 (of 36)
0xf0 RX_SAMPLE_DLY RX sample delay
0xf4 SPI_CTRLR0 SPI control
0xf8 TXD_DRIVE_EDGE TX drive edge
SSI: CTRLR0 Register
Offset: 0x00
Description
Control register 0
Table 593. CTRLR0
Register
Bits Name Description Type Reset
31:25 Reserved. - - -
24 SSTE Slave select toggle enable RW 0x0
23 Reserved. - - -
22:21 SPI_FRF SPI frame format
0x0 → Standard 1-bit SPI frame format; 1 bit per SCK, full-
duplex
0x1 → Dual-SPI frame format; two bits per SCK, half-
duplex
0x2 → Quad-SPI frame format; four bits per SCK, half-
duplex
RW 0x0
20:16 DFS_32 Data frame size in 32b transfer mode
Value of n → n+1 clocks per frame.
RW 0x00
15:12 CFS Control frame size
Value of n → n+1 clocks per frame.
RW 0x0
11 SRL Shift register loop (test mode) RW 0x0
10 SLV_OE Slave output enable RW 0x0
9:8 TMOD Transfer mode
0x0 → Both transmit and receive
0x1 → Transmit only (not for FRF == 0, standard SPI
mode)
0x2 → Receive only (not for FRF == 0, standard SPI mode)
0x3 → EEPROM read mode (TX then RX; RX starts after
control data TX’d)
RW 0x0
7 SCPOL Serial clock polarity RW 0x0
6 SCPH Serial clock phase RW 0x0
5:4 FRF Frame format RW 0x0
3:0 DFS Data frame size RW 0x0
SSI: CTRLR1 Register
Offset: 0x04
RP2040 Datasheet
4.10. SSI 620