Datasheet

Table Of Contents
Table 598. BAUDR
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 SCKDV SSI clock divider RW 0x0000
SSI: TXFTLR Register
Offset: 0x18
Description
TX FIFO threshold level
Table 599. TXFTLR
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 TFT Transmit FIFO threshold RW 0x00
SSI: RXFTLR Register
Offset: 0x1c
Description
RX FIFO threshold level
Table 600. RXFTLR
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 RFT Receive FIFO threshold RW 0x00
SSI: TXFLR Register
Offset: 0x20
Description
TX FIFO level
Table 601. TXFLR
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 TFTFL Transmit FIFO level RO 0x00
SSI: RXFLR Register
Offset: 0x24
Description
RX FIFO level
Table 602. RXFLR
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 RXTFL Receive FIFO level RO 0x00
SSI: SR Register
Offset: 0x28
RP2040 Datasheet
4.10. SSI 622