Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
The Instance IDs (top 4 bits of ID above) can be changed via a sysconfig register which may be useful in a multichip
application. However note that ID=0xf is reserved for the internal Rescue DP (see Section 2.3.4.2).
IO
Processors
Core0
DAP_0
DP-0 AP
Core1
SWD
Multidrop
arbiter
Rescue DP
SWD
SWCLK
SWDIO
DAP_1
DP-1 AP
sys_cfg.proc0_dap_instid
sys_cfg.proc1_dap_instidpam_restart
SWD
SWD
SWD
Figure 10. RP2040
Debugging
2.3.4.1. Software control of SWD pins
The SWD pins for Core 0 and Core 1 can be bit-banged via registers in syscfg (see DBGFORCE). This means that Core 1
could run a USB application that allows debug of Core 0, or similar.
2.3.4.2. Rescue DP
The Rescue DP (debug port) is available over the SWD bus and is only intended for use in the specific case where the
chip has locked up, for example if code has been programmed into flash which permanently halts the system clock: in
such a case, the normal debugger can not communicate with the processors to return the system to a working state, so
more drastic action is needed. A rescue is invoked by setting the CDBGPWRUPREQ bit in the Rescue DP’s CTRL/STAT
register.
This causes a hard reset of the chip (functionally similar to a power-on-reset), and sets a flag in the Chip Level Reset
block to indicate that a rescue reset took place. The bootrom checks this flag almost immediately in the initial boot
process (before watchdog, flash or USB boot), acknowledges by clearing the bit, then halts the processor. This leaves
the system in a safe state, with the system clock running, so that the debugger can reattach to the cores and load fresh
code.
For a practical example of using the Rescue DP, see the Hardware design with RP2040 book.
2.4. Cortex-M0+
ARM Documentation
Excerpted from the Cortex-M0+ Technical Reference Manual. Used with permission.
The ARM Cortex-M0+ processor is a very low gate count, highly energy efficient processor that is intended for
microcontroller and deeply embedded applications that require an area optimized, low-power processor.
2.4.1. Features
The ARM Cortex-M0+ processor features and benefits are:
•
Tight integration of system peripherals reduces area and development costs.
•
Thumb instruction set combines high code density with 32-bit performance.
•
Support for single-cycle I/O access.
RP2040 Datasheet
2.4. Cortex-M0+ 62