Datasheet

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Power control optimization of system components.
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Integrated sleep modes for low-power consumption.
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Fast code execution enables running the processor with a slower clock or increasing sleep mode time.
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Optimized code fetching for reduced flash and ROM power consumption.
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Hardware multiplier.
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Deterministic, high-performance interrupt handling for time-critical applications.
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Deterministic instruction cycle timing.
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Support for system level debug authentication.
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Serial Wire Debug reduces the number of pins required for debugging.
2.4.1.1. Interfaces
The interfaces included in the processor for external access include:
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External AHB-Lite interface to busfabric
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Debug Access Port (DAP)
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Single-cycle I/O Port to SIO peripherals
2.4.1.2. Configuration
Each processor is configured with the following features:
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Architectural clock gating (for power saving)
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Little Endian bus access
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Four Breakpoints
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Debug support (via 2-wire debug pins SWD/SWCLK)
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32-bit instruction fetch (to match 32-bit data bus)
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IOPORT (for low latency access to local peripherals (see SIO)
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26 interrupts
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8 MPU regions
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All registers reset on powerup
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Fast multiplier (MULS 32x32 single cycle)
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SysTick timer
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Vector Table Offset Register (VTOR)
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34 WIC (Wake-up Interrupt Controller) lines (32 IRQ and NMI, RXEV)
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DAP feature: Halt event support
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DAP feature: SerialWire debug interface (protocol 2 with multidrop support)
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DAP feature: Micro Trace Buffer (MTB) is not implemented
Architectural clock gating allows the processor core to support SLEEP and DEEPSLEEP power states by disabling the
clock to parts of the processor core. Note that power gating is not supported.
Each M0+ core has its own interrupt controller which can individually mask out interrupt sources as required. The same
interrupts are routed to both M0+ cores.
RP2040 Datasheet
2.4. Cortex-M0+ 63