Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Appendix B: Errata
Hardware blocks are listed alphabetically. Errata are listed numerically under the relevant block.
Bootrom
RP2040-E9
Reference
RP2040-E9
Summary
ROM bootloader cannot boot directly into XIP cache-as-SRAM
Description
The XIP cache can be used as an additional 16 kB SRAM bank when XIP caching is disabled (Section
2.6.3.1). The UF2 bootloader supports RAM-only UF2 binaries, which it loads directly into memory, and
enters via a watchdog reboot. A single UF2 binary can initialise both the XIP cache contents and main
system memory, and the cache is disabled by the bootloader, so that cache contents be written.
However, the watchdog reset re-enables the cache, so booting directly into the cache-as-SRAM alias
causes an immediate bus fault. The cache contents are preserved, but can not be accessed immediately
post-boot.
Workaround
Add code in main SRAM to re-disable XIP caching before accessing the cache-as-SRAM alias. When
entering a RAM-only UF2 binary, the bootloader selects the lowest loaded address in either main SRAM or
cache-as-SRAM as the entry point, preferring main SRAM if both are loaded.
Additionally, if the 0x15… segment is written immediately post-boot, a dummy read of the FLUSH register
is required, so that no cache-as-SRAM writes take place during the tag memory flush triggered by the
watchdog (see Section 2.6.3.2).
Affects
RP2040B0, RP2040B1
Fixed by
Documentation
Clocks
RP2040-E7
Reference
RP2040-E7
Summary
ROSC and XOSC COUNT registers are unreliable
Description
The ROSC and XOSC COUNT registers are intended to be used in the configuration of components like PHYs
and PLLs where microsecond scale delays are required and NOP loops are inadequate because the
clk_sys frequency is variable. However due to a synchronisation issue the ROSC:COUNT and
XOSC:COUNT registers are unreliable.
Workaround
Do not use ROSC:COUNT or XOSC:COUNT
Affects
RP2040B0, RP2040B1
Fixed by
Not fixed, do not use. These registers are not used by the C SDK.
RP2040 Datasheet
Bootrom 641