Datasheet

Description
The watchdog (Section 4.7) has a 24-bit counter, that decrements every tick, starting from a user defined
value set in LOAD register. There is a logic error which means the counter is decremented twice per tick,
instead of once per tick. In a recommended setup where the tick occurs at 1μs intervals, this halves the
maximum time between resetting the watchdog counter from ~16.7 seconds to ~8.3 seconds.
Workaround
Use double the desired value in LOAD.
Affects
RP2040B0, RP2040B1
Fixed by
Documentation, Software
XIP Flash
RP2040-E8
Reference
RP2040-E8
Summary
Race condition when aborting an XIP DMA stream and immediately starting a new stream
Description
The XIP DMA streaming hardware allows a linear sequences of flash reads to proceed in the background,
and be read by the DMA, without subjecting the DMA to the bus stalls caused by a normal XIP-window
access. A stream is begun by writing to the STREAM_ADDR register, followed by STREAM_CTR, and can
be aborted midway by writing 0 to STREAM_CTR.
When a stream is aborted in this way, there is sufficient time for software to load a new address and
begin a new stream whilst the final SPI/QSPI access of the aborted stream is still in progress. This
causes the newly-loaded stream address to be incremented once before the first data transfer of the new
stream sequence, so the entire stream takes place at a 4-byte offset.
Workaround
After clearing STREAM_CTR, immediately perform one dummy read from the uncached XIP window, e.g.
(void)*(io_ro_32*)XIP_NOCACHE_NOALLOC_BASE;. If an XIP stream transfer is still in progress, this dummy read
will stall until that transfer completes. It is then safe to begin a new stream by writing to STREAM_ADDR
followed by STREAM_CTR.
Affects
RP2040B0, RP2040B1
Fixed by
Documentation, Software
RP2040 Datasheet
XIP Flash 645