Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
2.4.1.3. ARM architecture
The processor implements the ARMv6-M architecture profile. See the ARMv6-M Architecture Reference Manual, and for
further details refer to the ARM Cortex M0+ Technical Reference Manual.
2.4.2. Functional Description
2.4.2.1. Overview
The Cortex-M0+ processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and
includes an NVIC component. It also has hardware debug, single-cycle I/O interfacing, and memory-protection
functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processors.
Figure 11 shows the functional blocks of the processor and surrounding blocks.
Cortex-M0+ subsystem
Clock
PMU MPUCortex M0+ Core
RESET CTRL
WIC DAP
Breakpoint and
watchpoint unit
Debugger
interface
NVIC
AHB-Lite Master
Single cycle IO Port
Serial Wire Debug
Reset
Interrupts
Bus Interface
HCLK
FCLK
DCLK
Figure 11. Cortex M0+
Functional block
diagram
2.4.2.2. Features
The M0+ features:
•
The ARMv6-M Thumb® instruction set.
•
Thumb-2 technology.
•
An ARMv6-M compliant 24-bit SysTick timer.
•
A 32-bit hardware multiplier. This is the standard single-cycle multiplier
•
The ability to have deterministic, fixed-latency, interrupt handling.
•
Load/store multiple instructions that can be abandoned and restarted to facilitate rapid interrupt handling.
•
C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-
ABI) compliant exception model that enables the use of pure C functions as interrupt handlers.
•
Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from
interrupt sleep-on-exit feature.
2.4.2.3. NVIC features
The Nested Vectored Interrupt Controller (NVIC) features are:
•
26 external interrupt inputs, each with four levels of priority.
•
Dedicated Non-Maskable Interrupt (NMI) input (which can be driven from any standard interrupt source)
•
Support for both level-sensitive and pulse-sensitive interrupt lines.
RP2040 Datasheet
2.4. Cortex-M0+ 64