Datasheet

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Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.
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Relocatable vector table.

NOTE
The NVIC supports hardware nesting of exceptions, e.g. an interrupt handler may itself be interrupted if a higher-
priority interrupt request arrives whilst the handler is running.
Further details available in Section 2.4.5.
2.4.2.4. Debug features
Debug features are:
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Four hardware breakpoints.
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Two watchpoints.
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Program Counter Sampling Register (PCSR) for non-intrusive code profiling.
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Single step and vector catch capabilities.
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Support for unlimited software breakpoints using BKPT instruction.
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Non-intrusive access to core peripherals and zero-waitstate system slaves through a compact bus matrix. A
debugger can access these devices, including memory, even when the processor is running.
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Full access to core registers when the processor is halted.
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CoreSight compliant debug access through a Debug Access Port (DAP) supporting Serial Wire debug connections.
2.4.2.4.1. Debug Access Port
The processor is implemented with a low gate count Debug Access Port (DAP). The low gate count Debug Access Port
(DAP) provides a Serial Wire debug-port, and connects to the processor slave port to provide full system-level debug
access. For more information on DAP, see the ADI v5.1 version of the ARM Debug Interface v5, Architecture
Specification
2.4.2.5. MPU features
Memory Protection Unit (MPU) features are:
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Eight user-configurable memory regions.
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Eight sub-region disables per region.
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Execute never (XN) support.
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Default memory map support.
Further details available in Section 2.4.6.
2.4.2.6. AHB-Lite interface
Transactions on the AHB-Lite interface are always marked as non-sequential. Processor accesses and debug accesses
share the external interface to external AHB peripherals. The processor accesses take priority over debug accesses.
Any vendor-specific components can populate this bus.
RP2040 Datasheet
2.4. Cortex-M0+ 65