Datasheet

Note
If PRIMASK.PM is set to 1, an asynchronous exception that has a higher group priority than any active exception
results in a WFI instruction exit. If the group priority of the exception is less than or equal to the execution group
priority, the exception is ignored.
•
If debug is enabled, a debug event.
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A WFI wakeup event.
The WFI instruction completes when the hardware detects a WFI wake up event.
The processor recognizes WFI wake up events only after issuing the WFI instruction.
2.4.2.8.4. Wakeup Interrupt Controller
The Wakeup Interrupt Controller (WIC) is used to wake the processor from a DEEPSLEEP state as controlled by the SCR
register. In a DEEPSLEEP state clocks to the processor core and NVIC are not running. It can take a few cycles to wake
from a DEEPSLEEP state.
The WIC takes inputs from the receive event signal (from the other processor), 32 interrupts lines, and NMI.
For more power saving, RP2040 supports system level power saving modes as defined in Section 2.11 which also
includes code examples.
2.4.2.9. Reset Control
The Cortex M0+ Reset Control block controls the following resets:
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Debug reset
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M0+ core reset
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PMU reset
After power up, both processors are released from reset (see details in Section 2.13.2). This releases reset to Debug,
M0+ core and PMU.
Once running, resets can be triggered from the Debugger, NVIC (using AIRCR.SYSRESETREQ), or the RP2040 Power On State
Machine controller (see details in Section 2.13). The NVIC only resets the Cortex-M0+ processor core (not the Debug or
PMU), whereas the Power On State Machine controller can reset the processor subsystem which asserts all resets in
the subsystem (Debug, M0+ core, PMU).
2.4.3. Programmer’s model
2.4.3.1. About the programmer’s model
The ARMv6-M Architecture Reference Manual provides a complete description of the programmer’s model. This chapter
gives an overview of the Cortex-M0+ programmer’s model that describes the implementation-defined options. It also
contains the ARMv6-M Thumb instructions it uses and their cycle counts for the processor. Additional details are in
following chapters
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Section 2.4.4 summarizes the system control features of the programmer’s model.
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Section 2.4.5 summarizes the NVIC features of the programmer’s model.
•
Section 2.3.4 summarizes the Debug features of the programmer’s model.
RP2040 Datasheet
2.4. Cortex-M0+ 68