Datasheet

2.4.3.2. Modes of operation and execution
See the ARMv6-M Architecture Reference Manual for information about the modes of operation and execution.
2.4.3.3. Instruction set summary
The processor implements the ARMv6-M Thumb instruction set, including a number of 32-bit instructions that use
Thumb-2 technology. The ARMv6-M instruction set comprises:
•
All of the 16-bit Thumb instructions from ARMv7-M excluding CBZ, CBNZ and IT.
•
The 32-bit Thumb instructions BL, DMB, DSB, ISB, MRS and MSR.
Table 81 shows the Cortex-M0+ instructions and their cycle counts. The cycle counts are based on a system with zero
wait-states.
Table 81. Cortex-M0+
instruction summary
Operation Description Assembler Cycles
Move 8-bit immediate
MOVS Rd, #<imm>
1
Lo to Lo
MOVS Rd, Rm
1
Any to Any
MOV Rd, Rm
1
Any to PC
MOV PC, Rm
2
Add 3-bit immediate
ADDS Rd, Rn, #<imm>
1
All registers Lo
ADDS Rd, Rn, Rm
1
Any to Any
ADD Rd, Rd, Rm
1
Any to PC
ADD PC, PC, Rm
2
8-bit immediate
ADDS Rd, Rd, #<imm>
1
With carry
ADCS Rd, Rd, Rm
1
Immediate to SP
ADD SP, SP, #<imm>
1
Form address from SP
ADD Rd, SP, #<imm>
1
Form address from PC
ADR Rd, <label>
1
Subtract Lo and Lo
SUBS Rd, Rn, Rm
1
3-bit immediate
SUBS Rd, Rn, #<imm>
1
8-bit immediate
SUBS Rd, Rd, #<imm>
1
With carry
SBCS Rd, Rd, Rm
1
Immediate from SP
SUB SP, SP, #<imm>
1
Negate
RSBS Rd, Rn, #0
1
Multiply Multiply
MULS Rd, Rm, Rd
1
Compare Compare
CMP Rn, Rm
1
Negative
CMN Rn, Rm
1
Immediate
CMP Rn, #<imm>
1
Logical AND
ANDS Rd, Rd, Rm
1
Exclusive OR
EORS Rd, Rd, Rm
1
OR
ORRS Rd, Rd, Rm
1
RP2040 Datasheet
2.4. Cortex-M0+ 69