Datasheet

Operation Description Assembler Cycles
Bit clear
BICS Rd, Rd, Rm
1
Move NOT
MVNS Rd, Rm
1
AND test
TST Rn, Rm
1
Shift Logical shift left by immediate
LSLS Rd, Rm, #<shift>
1
Logical shift left by register
LSLS Rd, Rd, Rs
1
Logical shift right by immediate
LSRS Rd, Rm, #<shift>
1
Logical shift right by register
LSRS Rd, Rd, Rs
1
Arithmetic shift right
ASRS Rd, Rm, #<shift>
1
Arithmetic shift right by register
ASRS Rd, Rd, Rs
1
Rotate Rotate right by register
RORS Rd, Rd, Rs
1
Load Word, immediate offset
LDR Rd, [Rn, #<imm>]
2 or 1
a
Halfword, immediate offset
LDRH Rd, [Rn, #<imm>]
2 or 1
a
Byte, immediate offset
LDRB Rd, [Rn, #<imm>]
2 or 1
a
Word, register offset
LDR Rd, [Rn, Rm]
2 or 1
a
Halfword, register offset
LDRH Rd, [Rn, Rm]
2 or 1
a
Signed halfword, register offset
LDRSH Rd, [Rn, Rm]
2 or 1
a
Byte, register offset
LDRB Rd, [Rn, Rm]
2 or 1
a
Signed byte, register offset
LDRSB Rd, [Rn, Rm]
2 or 1
a
PC-relative
LDR Rd, <label>
2 or 1
a
SP-relative
LDR Rd, [SP, #<imm>]
2 or 1
a
Multiple, excluding base
LDM Rn!, {<loreglist>}
1+N
b
Multiple, including base
LDM Rn, {<loreglist>}
1+N
b
Store Word, immediate offset
STR Rd, [Rn, #<imm>]
2 or 1
a
Halfword, immediate offset
STRH Rd, [Rn, #<imm>]
2 or 1
a
Byte, immediate offset
STRB Rd, [Rn, #<imm>]
2 or 1
a
Word, register offset
STR Rd, [Rn, Rm]
2 or 1
a
Halfword, register offset
STRH Rd, [Rn, Rm]
2 or 1
a
Byte, register offset
STRB Rd, [Rn, Rm]
2 or 1
a
SP-relative
STR Rd, [SP, #<imm>]
2 or 1
a
Multiple
STM Rn!, {<loreglist>}
1+N
b
Push Push
PUSH {<loreglist>}
1+N
b
Push with link register
PUSH {<loreglist>, LR}
1+N
c
Pop Pop
POP {<loreglist>}
1+N
b
Pop and return
POP {<loreglist>, PC}
3+N
c
Branch Conditional
B<cc> <label>
1 or 2
d
Unconditional
B <label>
2
RP2040 Datasheet
2.4. Cortex-M0+ 70