Datasheet

Operation Description Assembler Cycles
With link
BL <label>
3
With exchange
BX Rm
2
With link and exchange
BLX Rm
2
Extend Signed halfword to word
SXTH Rd, Rm
1
Signed byte to word
SXTB Rd, Rm
1
Unsigned halfword
UXTH Rd, Rm
1
Unsigned byte
UXTB Rd, Rm
1
Reverse Bytes in word
REV Rd, Rm
1
Bytes in both halfwords
REV16 Rd, Rm
1
Signed bottom half word
REVSH Rd, Rm
1
State change Supervisor Call
SVC #<imm>
-
e
Disable interrupts
CPSID i
1
Enable interrupts
CPSIE i
1
Read special register
MRS Rd, <specreg>
3
Write special register
MSR <specreg>, Rn
3
Breakpoint
BKPT #<imm>
-
e
Hint Send-Event
SEV
1
Wait For Event
WFE
2
f
Wait For Interrupt
WFI
2
f
Yield
YIELD
1
f
No operation
NOP
1
Barriers Instruction synchronization
ISB
3
Data memory
DMB
3
Data synchronization
DSB
3
Table Notes
a
2 if to AHB interface or SCS, 1 if to single-cycle I/O port.
b
N is the number of elements in the list.
c
N is the number of elements in the list including PC or LR.
d
2 if taken, 1 if not-taken.
e
Cycle count depends on processor and debug configuration.
f
Excludes time spent waiting for an interrupt or event.
g
Executes as NOP.
See the ARMv6-M Architecture Reference Manual for more information about the ARMv6-M Thumb instructions.
2.4.3.4. Memory model
The processor contains a bus matrix that arbitrates the processor core and Debug Access Port (DAP) memory
accesses to both the external memory system and to the internal NVIC and debug components.
Priority is always given to the processor to ensure that any debug accesses are as non-intrusive as possible. For a zero
RP2040 Datasheet
2.4. Cortex-M0+ 71