Datasheet

wait-state system, all debug accesses to system memory, NVIC, and debug resources are completely non-intrusive for
typical code execution.
The system memory map is ARMv6-M architecture compliant, and is common both to the debugger and processor
accesses. Transactions are routed as follows:
•
All accesses below 0xd0000000 or above 0xefffffff appear as AHB-Lite transactions on the AHB-Lite master port of
the processor.
•
Accesses in the range 0xd0000000 to 0xdfffffff are handled by the SIO.
•
Accesses in the range 0xe0000000 to 0xefffffff are handled within the processor and do not appear on the AHB-Lite
master port of the processor.
The processor supports only word size accesses in the range 0xd0000000 - 0xefffffff.
Table 82 shows the code, data, and device suitability for each region of the default memory map. This is the memory
map used by implementations when the MPU is disabled. The attributes and permissions of all regions, except that
targeting the Cortex-M0+ NVIC and debug components, can be modified using an implemented MPU.
Table 82. M0+ Default
memory map usage
Address range Code Data Device
0xf0000000 - 0xffffffff
No No Yes
0xe0000000 - 0xefffffff
No No No
a
0xa0000000 - 0xdfffffff
No No Yes
0x60000000 - 0x9fffffff
Yes Yes No
0x40000000 - 0x5fffffff
No No Yes
0x20000000 - 0x3fffffff
Yes Yes No
0x00000000 - 0x1fffffff
Yes Yes No
a
. Space reserved for Cortex-M0+ NVIC and debug components.
Note
Regions not marked as suitable for code behave as eXecute-Never (XN) and generate a HardFault exception if code
attempts to execute from this location.
See the ARMv6-M Architecture Reference Manual for more information about the memory model.
2.4.3.5. Processor core registers summary
Table 83 shows the processor core register set summary. Each of these registers is 32 bits wide.
Table 83. M0+
processor core
register set summary
Name Description
R0-R12 R0-R12 are general-purpose registers for data operations.
MSP/PSP (R13) The Stack Pointer (SP) is register R13. In Thread mode,
the CONTROL register indicates the stack pointer to use,
Main Stack Pointer (MSP) or Process Stack Pointer (PSP).
LR (R14) The Link Register (LR) is register R14. It stores the return
information for subroutines, function calls, and
exceptions.
PC (R15) The Program Counter (PC) is register R15. It contains the
current program address.
RP2040 Datasheet
2.4. Cortex-M0+ 72