Datasheet

Name Description
PSR The Program Status Register (PSR) combines:
•
Application Program Status Register (APSR).
•
Interrupt Program Status Register (IPSR).
•
Execution Program Status Register (EPSR).
These registers provide different views of the PSR.
PRIMASK The PRIMASK register prevents activation of all
exceptions with configurable priority.
CONTROL The CONTROL register controls the stack used, the code
privilege level, when the processor is in Thread mode.
Note
See the ARMv6-M Architecture Reference Manual for information about the processor core registers and their
addresses, access types, and reset values.
2.4.3.6. Exceptions
This section describes the exception model of the processor.
2.4.3.6.1. Exception handling
The processor implements advanced exception and interrupt handling, as described in the ARMv6-M Architecture
Reference Manual. To minimize interrupt latency, the processor abandons any load-multiple or store-multiple instruction
to take any pending interrupt. On return from the interrupt handler, the processor restarts the load-multiple or store-
multiple instruction from the beginning.
This means that software must not use load-multiple or store-multiple instructions when a device is accessed in a
memory region that is read-sensitive or sensitive to repeated writes. The software must not use these instructions in
any case where repeated reads or writes might cause inconsistent results or unwanted side-effects.
The processor implementation can ensure that a fixed number of cycles are required for the NVIC to detect an interrupt
signal and the processor fetch the first instruction of the associated interrupt handler. If this is done, the highest priority
interrupt is jitter-free. This will depend on where the interrupt handler is located and if another higher priority master is
accessing that memory. SRAM4 and SRAM5 are provided that may be allocated to interrupt handlers for each processor
so this is jitter-free.
To reduce interrupt latency and jitter, the Cortex-M0+ processor implements both interrupt late-arrival and interrupt tail-
chaining mechanisms, as defined by the ARMv6-M architecture. The worst case interrupt latency, for the highest priority
active interrupt in a zero wait-state system not using jitter suppression, is 15 cycles.
The processor exception model has the following implementation-defined behaviour in addition to the architecture
specified behaviour:
•
Exceptions on stacking from HardFault to NMI lockup at NMI priority.
•
Exceptions on unstacking from NMI to HardFault lockup at HardFault priority.
2.4.4. System control
RP2040 Datasheet
2.4. Cortex-M0+ 73