Datasheet

2.4.4.1. System control register summary
Table 84 gives the system control registers. Each of these registers is 32 bits wide.
Table 84. M0+ System
control registers
Name Description
SYST_CSR SysTick Control and Status Register
SYST_RVR SysTick Reload Value Register
SYST_CVR SysTick Current Value Register
SYST_CALIB SysTick Calibration value Register
CPUID See CPUID Register
ICSR Interrupt Control State Register
AIRCR Application Interrupt and Reset Control Register
CCR Configuration and Control Register
SHPR2 System Handler Priority Register
SHPR3 System Handler Priority Register
SHCSR System Handler Control and State Register
VTOR Vector table Offset Register
ACTLR Auxiliary Control Register
Note
•
All system control registers are only accessible using word transfers. Any attempt to read or write a halfword
or byte is Unpredictable.
•
See the List of Registers or ARMv6-M Architecture Reference Manual for more information about the system
control registers, and their addresses and access types, and reset values.
2.4.4.1.1. CPUID Register
The CPUID contains the part number, version, and implementation information that is specific to the processor.

IMPORTANT
This standard internal Arm register contains information about the type of processor. It should not be confused with
CPUID (Section 2.3.1.1), an RP2040 SIO register which reads as 0 on core 0 and 1 on core 1.
2.4.5. NVIC
2.4.5.1. About the NVIC
External interrupt signals connect to the Nested Vectored Interrupt Controller (NVIC), and the NVIC prioritizes the
interrupts. Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely
coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts.
RP2040 Datasheet
2.4. Cortex-M0+ 74