Datasheet

Description
Use the SysTick Control and Status Register to enable the SysTick features.
Table 88. SYST_CSR
Register
Bits Name Description Type Reset
31:17 Reserved. - - -
16 COUNTFLAG Returns 1 if timer counted to 0 since last time this was
read. Clears on read by application or debugger.
RO 0x0
15:3 Reserved. - - -
2 CLKSOURCE SysTick clock source. Always reads as one if SYST_CALIB
reports NOREF.
Selects the SysTick timer clock source:
0 = External reference clock.
1 = Processor clock.
RW 0x0
1 TICKINT Enables SysTick exception request:
0 = Counting down to zero does not assert the SysTick
exception request.
1 = Counting down to zero to asserts the SysTick
exception request.
RW 0x0
0 ENABLE Enable SysTick counter:
0 = Counter disabled.
1 = Counter enabled.
RW 0x0
M0PLUS: SYST_RVR Register
Offset: 0xe014
Description
Use the SysTick Reload Value Register to specify the start value to load into the current value register when the
counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect
because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this
register is UNKNOWN.
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example,
if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.
Table 89. SYST_RVR
Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:0 RELOAD Value to load into the SysTick Current Value Register
when the counter reaches 0.
RW 0x000000
M0PLUS: SYST_CVR Register
Offset: 0xe018
Description
Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is
UNKNOWN.
RP2040 Datasheet
2.4. Cortex-M0+ 78