Datasheet

Bits Name Description Type Reset
31 NMIPENDSET Setting this bit will activate an NMI. Since NMI is the
highest priority exception, it will activate as soon as it is
registered.
NMI set-pending bit.
Write:
0 = No effect.
1 = Changes NMI exception state to pending.
Read:
0 = NMI exception is not pending.
1 = NMI exception is pending.
Because NMI is the highest-priority exception, normally
the processor enters the NMI
exception handler as soon as it detects a write of 1 to this
bit. Entering the handler then clears
this bit to 0. This means a read of this bit by the NMI
exception handler returns 1 only if the
NMI signal is reasserted while the processor is executing
that handler.
RW 0x0
30:29 Reserved. - - -
28 PENDSVSET PendSV set-pending bit.
Write:
0 = No effect.
1 = Changes PendSV exception state to pending.
Read:
0 = PendSV exception is not pending.
1 = PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV
exception state to pending.
RW 0x0
27 PENDSVCLR PendSV clear-pending bit.
Write:
0 = No effect.
1 = Removes the pending state from the PendSV
exception.
RW 0x0
26 PENDSTSET SysTick exception set-pending bit.
Write:
0 = No effect.
1 = Changes SysTick exception state to pending.
Read:
0 = SysTick exception is not pending.
1 = SysTick exception is pending.
RW 0x0
25 PENDSTCLR SysTick exception clear-pending bit.
Write:
0 = No effect.
1 = Removes the pending state from the SysTick
exception.
This bit is WO. On a register read its value is Unknown.
RW 0x0
24 Reserved. - - -
RP2040 Datasheet
2.4. Cortex-M0+ 85