Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
23 ISRPREEMPT The system can only access this bit when the core is
halted. It indicates that a pending interrupt is to be taken
in the next running cycle. If C_MASKINTS is clear in the
Debug Halting Control and Status Register, the interrupt is
serviced.
RO 0x0
22 ISRPENDING External interrupt pending flag RO 0x0
21 Reserved. - - -
20:12 VECTPENDING Indicates the exception number for the highest priority
pending exception: 0 = no pending exceptions. Non zero =
The pending state includes the effect of memory-mapped
enable and mask registers. It does not include the
PRIMASK special-purpose register qualifier.
RO 0x000
11:9 Reserved. - - -
8:0 VECTACTIVE Active exception number field. Reset clears the
VECTACTIVE field.
RO 0x000
M0PLUS: VTOR Register
Offset: 0xed08
Description
The VTOR holds the vector table offset address.
Table 106. VTOR
Register
Bits Name Description Type Reset
31:8 TBLOFF Bits [31:8] of the indicate the vector table offset address. RW 0x000000
7:0 Reserved. - - -
M0PLUS: AIRCR Register
Offset: 0xed0c
Description
Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state
information from debug halt mode, request a system reset.
Table 107. AIRCR
Register
Bits Name Description Type Reset
31:16 VECTKEY Register key:
Reads as Unknown
On writes, write 0x05FA to VECTKEY, otherwise the write
is ignored.
RW 0x0000
15 ENDIANESS Data endianness implemented:
0 = Little-endian.
RO 0x0
14:3 Reserved. - - -
RP2040 Datasheet
2.4. Cortex-M0+ 86