Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
2 SYSRESETREQ Writing 1 to this bit causes the SYSRESETREQ signal to
the outer system to be asserted to request a reset. The
intention is to force a large system reset of all major
components except for debug. The C_HALT bit in the
DHCSR is cleared as a result of the system reset
requested. The debugger does not lose contact with the
device.
RW 0x0
1 VECTCLRACTIVE Clears all active state information for fixed and
configurable exceptions. This bit: is self-clearing, can only
be set by the DAP when the core is halted. When set:
clears all active exception status of the processor, forces
a return to Thread mode, forces an IPSR of 0. A debugger
must re-initialize the stack.
RW 0x0
0 Reserved. - - -
M0PLUS: SCR Register
Offset: 0xed10
Description
System Control Register. Use the System Control Register for power-management functions: signal to the system
when the processor can enter a low power state, control how the processor enters and exits low power states.
Table 108. SCR
Register
Bits Name Description Type Reset
31:5 Reserved. - - -
4 SEVONPEND Send Event on Pending bit:
0 = Only enabled interrupts or events can wakeup the
processor, disabled interrupts are excluded.
1 = Enabled events and all interrupts, including disabled
interrupts, can wakeup the processor.
When an event or interrupt becomes pending, the event
signal wakes up the processor from WFE. If the
processor is not waiting for an event, the event is
registered and affects the next WFE.
The processor also wakes up on execution of an SEV
instruction or an external event.
RW 0x0
3 Reserved. - - -
2 SLEEPDEEP Controls whether the processor uses sleep or deep sleep
as its low power mode:
0 = Sleep.
1 = Deep sleep.
RW 0x0
1 SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode
to Thread mode:
0 = Do not sleep when returning to Thread mode.
1 = Enter sleep, or deep sleep, on return from an ISR to
Thread mode.
Setting this bit to 1 enables an interrupt driven application
to avoid returning to an empty main application.
RW 0x0
0 Reserved. - - -
RP2040 Datasheet
2.4. Cortex-M0+ 87