Datasheet

M0PLUS: CCR Register
Offset: 0xed14
Description
The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to
result in a Hard Fault.
Table 109. CCR
Register
Bits Name Description Type Reset
31:10 Reserved. - - -
9 STKALIGN Always reads as one, indicates 8-byte stack alignment on
exception entry. On exception entry, the processor uses
bit[9] of the stacked PSR to indicate the stack alignment.
On return from the exception it uses this stacked bit to
restore the correct stack alignment.
RO 0x0
8:4 Reserved. - - -
3 UNALIGN_TRP Always reads as one, indicates that all unaligned accesses
generate a HardFault.
RO 0x0
2:0 Reserved. - - -
M0PLUS: SHPR2 Register
Offset: 0xed1c
Description
System handlers are a special class of exception handler that can have their priority set to any of the priority levels.
Use the System Handler Priority Register 2 to set the priority of SVCall.
Table 110. SHPR2
Register
Bits Name Description Type Reset
31:30 PRI_11 Priority of system handler 11, SVCall RW 0x0
29:0 Reserved. - - -
M0PLUS: SHPR3 Register
Offset: 0xed20
Description
System handlers are a special class of exception handler that can have their priority set to any of the priority levels.
Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.
Table 111. SHPR3
Register
Bits Name Description Type Reset
31:30 PRI_15 Priority of system handler 15, SysTick RW 0x0
29:24 Reserved. - - -
23:22 PRI_14 Priority of system handler 14, PendSV RW 0x0
21:0 Reserved. - - -
M0PLUS: SHCSR Register
Offset: 0xed24
RP2040 Datasheet
2.4. Cortex-M0+ 88