Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Description
Use the System Handler Control and State Register to determine or clear the pending status of SVCall.
Table 112. SHCSR
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15 SVCALLPENDED Reads as 1 if SVCall is Pending. Write 1 to set pending
SVCall, write 0 to clear pending SVCall.
RW 0x0
14:0 Reserved. - - -
M0PLUS: MPU_TYPE Register
Offset: 0xed90
Description
Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU
supports.
Table 113. MPU_TYPE
Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:16 IREGION Instruction region. Reads as zero as ARMv6-M only
supports a unified MPU.
RO 0x00
15:8 DREGION Number of regions supported by the MPU. RO 0x08
7:1 Reserved. - - -
0 SEPARATE Indicates support for separate instruction and data
address maps. Reads as 0 as ARMv6-M only supports a
unified MPU.
RO 0x0
M0PLUS: MPU_CTRL Register
Offset: 0xed94
Description
Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is
enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.
Table 114. MPU_CTRL
Register
Bits Name Description Type Reset
31:3 Reserved. - - -
2 PRIVDEFENA Controls whether the default memory map is enabled as a
background region for privileged accesses. This bit is
ignored when ENABLE is clear.
0 = If the MPU is enabled, disables use of the default
memory map. Any memory access to a location not
covered by any enabled region causes a fault.
1 = If the MPU is enabled, enables use of the default
memory map as a background region for privileged
software accesses.
When enabled, the background region acts as if it is region
number -1. Any region that is defined and enabled has
priority over this default map.
RW 0x0
RP2040 Datasheet
2.4. Cortex-M0+ 89