Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
4 VALID On writes, indicates whether the write must update the
base address of the region identified by the REGION field,
updating the MPU_RNR to indicate this new region.
Write:
0 = MPU_RNR not changed, and the processor:
Updates the base address for the region specified in the
MPU_RNR.
Ignores the value of the REGION field.
1 = The processor:
Updates the value of the MPU_RNR to the value of the
REGION field.
Updates the base address for the region specified in the
REGION field.
Always reads as zero.
RW 0x0
3:0 REGION On writes, specifies the number of the region whose base
address to update provided VALID is set written as 1. On
reads, returns bits [3:0] of MPU_RNR.
RW 0x0
M0PLUS: MPU_RASR Register
Offset: 0xeda0
Description
Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region
identified by MPU_RNR, and enable that region.
Table 117. MPU_RASR
Register
Bits Name Description Type Reset
31:16 ATTRS The MPU Region Attribute field. Use to define the region
attribute control.
28 = XN: Instruction access disable bit:
0 = Instruction fetches enabled.
1 = Instruction fetches disabled.
26:24 = AP: Access permission field
18 = S: Shareable bit
17 = C: Cacheable bit
16 = B: Bufferable bit
RW 0x0000
15:8 SRD Subregion Disable. For regions of 256 bytes or larger, each
bit of this field controls whether one of the eight equal
subregions is enabled.
RW 0x00
7:6 Reserved. - - -
5:1 SIZE Indicates the region size. Region size in bytes =
2^(SIZE+1). The minimum permitted value is 7 (b00111) =
256Bytes
RW 0x00
0 ENABLE Enables the region. RW 0x0
2.5. DMA
The RP2040 Direct Memory Access (DMA) controller has separate read and write master connections to the bus fabric,
and performs bulk data transfers on a processor’s behalf. This leaves processors free to attend to other tasks, or enter
low-power sleep states. The data throughput of the DMA is also significantly higher than one of RP2040’s processors.
RP2040 Datasheet
2.5. DMA 91