Datasheet

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Bit reversal
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Byte swap
These manipulations do not affect the CRC calculation, just how the data is presented in the result register.
2.5.5.3. Channel Abort
It is possible for a channel to get into an irrecoverable state: e.g. if commanded to transfer more data than a peripheral
will ever request, it will never complete. Clearing the CTRL.EN bit merely pauses the channel, and does not solve the
problem. This should not occur under normal circumstances, but it is important that there is a mechanism to recover
without simply hard-resetting the entire DMA block.
The CHAN_ABORT register forces channels to complete early. There is one bit for each channel, and writing a 1
terminates that channel. This clears the transfer counter and forces the channel into an inactive state.

NOTE
Aborting a DMA channel does not cause assertion of its IRQ; abort does not count as a completion for IRQ purposes.
At the point where the corresponding CHAN_ABORT register bit is set high, a channel may have bus transfers currently
in flight between the read and write master, and these transfers cannot be revoked. Once set, a bit in CHAN_ABORT
stays high until these transfers complete, and the channel reaches a safe state, which generally takes only a few cycles.
The correct procedure is to write a bitmap into CHAN_ABORT of the channels you wish to terminate, and then poll the
register until it reads all-zeroes.

CAUTION
Following an abort, the channel must not be restarted until the corresponding bit in CHAN_ABORT is once again
seen low. Starting the channel
2.5.5.4. Debug
Debug registers are available for each DMA channel to show the dreq counter DBG_CTDDREQ and next transfer count
DBG_TCR. These can also be used to reset a DMA channel if required.
2.5.6. Example Use Cases
2.5.6.1. Using Interrupts to Reconfigure a Channel
When a channel finishes a block of transfers, it becomes available for making more transfers. Software detects that the
channel is no longer busy, and reconfigures and restarts the channel. One approach is to poll the CTRL_BUSY bit until the
channel is done, but this loses one of the key advantages of the DMA, namely that it does not have to operate in
lockstep with a processor. By setting the correct bit in INTE0 or INTE1, we can instruct the DMA to raise one of its two
interrupt request lines when a given channel completes. Rather than repeatedly asking if a channel is done, we are told.
RP2040 Datasheet
2.5. DMA 98