Datasheet

IMX219PQH5-C
24
Table 9 2-wire Serial Communication AC Timing (Fast mode)
Item
Symbol
Min.
Max.
Unit
SCL clock frequency ( INCK[fSCK] = 6 to 27 MHz)
f
SCL
0
400
kHz
Rise time (SDA and SCL)
t
R
―
300
ns
Fall time (SDA and SCL)
t
F
―
300
ns
Hold time (start condition)
t
HDSTA
0.6
―
µs
Setup time (rep.-start condition)
t
SUSTA
0.6
―
µs
Setup time (stop condition)
t
SUSTO
0.6
―
µs
Data setup time
t
SUDAT
100
―
ns
Data hold time
t
HDDAT
0
0.9
µs
Bus free time between Stop and Start condition
t
BUF
1.3
µs
Low period of the SCL clock
t
LOW
1.3
µs
High period of the SCL clock
t
HIGH
0.6
µs
3-1-4 2-wire serial communication register map
3-1-4-1 Description of 2-wire communication register map
In 2-wire serial communication, there is a 16-bit address space as follows. In IMX219PQH5-C, there are
partially unreadable registers, which is described in Register map. If reading unreadable registers, the value to
be read is 00h.
Table 10 2-wire Serial Communication Register Map Address Areas
Address Area
Description
0x0000 - 0x0fff
Configuration register
0x1000 - 0x1fff
Parameter limit register
Read Only and Static resister
0x3000 - 0xffff
Manufacture specific register