Datasheet
Table Of Contents
- Description
- Features
- Device Structure
- USE RESTRICTION NOTICE
- 1. Block Diagram and Pin Configuration
- 2. Pixel Signal Output Specifications
- 3. Control Registers
- 3-1 2-wire Serial Communication Operation Specifications
- 3-2 2-wire Serial Communication Register Map (Configuration register, Parameter limit register)
- 3-3 Parameter Limit Registers – [0x1000-0x1FFF] (Read Only and Static)
- 3-4 Manufacturer Specific Registers – [0x3000-0x5FFF ]
- 3-5 Frame Bank A and Bank B specific output samples
- 4. Output Data Format
- 6. On Chip Image Processing
- 7. NVM Memory Map
- 8. How to operate IMX219PQH5-C
- 9. Other Functions
- 10. Electrical Characteristics
- 11. Spectral Sensitivity Characteristic
- 12. Image Sensor Characteristics
- 13. Measurement Method for Image Sensor Characteristics
- 14. Spot Pixel Specification
- 15. Notice on White Pixels Specifications
- 16. Chief Ray Angle Characteristics
- 17. Connection Example
- 18. Notes On Handling
IMX219PQH5-C
60
5-8-2 Digital gain settings
The IMX219PQH5-C can set the digital gain for global. The registers required to set the digital gain are as follows.
Table 24 Digital Gain Settings
CCI register name
Upper byte address
(Setting range:1 to15)
Lower byte address
(Setting range:0 to 255)
DIG_GAIN_GLOBAL_A
0x0158
0x0159
DIG_GAIN_GLOBAL_B
0x0258
0x0259
Each register is comprised of 2 bytes, with the upper byte [15:8] setting the integer portion and the lower byte [7:0]
setting the fractional portion of the gain. The gain for global is obtained by the following equation.
The upper byte can be set to a value between 1 and 15, and the lower byte to a value between 0 and 255.
Therefore, the digital gain setting range for global is as follows.
When gain is considered in log linear scale, the adjustment steps are large at low gain and extremely small at high
gain. The register values are shown on the following page in case of the gain in log linear manner in 0.1 dB steps.