Data Sheet

262

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

23.9 Register Description

23.9.1 ADMUX – ADC Multiplexer Selection Register

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 23-3. If these bits are

changed during a conversion, the change will not go in effect until this conversion is complete

(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external

reference voltage is being applied to the AREF pin.

•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a complete description of this bit, see ”ADCL and ADCH – The ADC Data Register” on

page 265.

• Bit 4 – Res: Reserved Bit

This bit is an unused bit in the ATmega48PA/88PA/168PA/328P, and will always read as zero.

• Bits 3:0 – MUX3:0: Analog Channel Selection Bits

The value of these bits selects which analog inputs are connected to the ADC. See Table 23-4

for details.

If these bits are changed during a conversion, the change will not go in effect until this

conversion is complete (ADIF in ADCSRA is set).

Bit 76543210

(0x7C) REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 ADMUX

Read/Write R/W R/W R/W R R/W R/W R/W R/W

Initial Value00000000

Table 23-3. Voltage Reference Selections for ADC

REFS1 REFS0 Voltage Reference Selection

0 0 AREF, Internal V

ref

turned off

with external capacitor at AREF pin

10Reserved

1 1 Internal 1.1V Voltage Reference with external capacitor at AREF pin