ARM 7TDMI Data Sheet Issued: August 1995 Copyright Advanced RISC Machines Ltd (ARM) 1995 All rights reserved Proprietary Notice ARM, the ARM Powered logo, EmbeddedICE, BlackICE and ICEbreaker are trademarks of Advanced RISC Machines Ltd. Neither the whole nor any part of the information contained in, or the product described in, this datasheet may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.
Key: Open Access No confidentiality To enable document tracking, the document number has two codes: Major release A B etc Pre-release First release Second release etc Draft Status Full and complete First Draft Second Draft etc Embargoed (date given) Open Access draft1 draft2 etc E ii ARM7TDMI Data Sheet ARM DDI 0029E
1 11 TOC 1 2 3 Introduction 1-1 1.1 1.2 1.3 1.4 1.5 1-2 1-2 1-4 1-5 1-6 Introduction ARM7TDMI Architecture ARM7TDMI Block Diagram ARM7TDMI Core Diagram ARM7TDMI Functional Diagram Signal Description 2-1 2.1 Signal Description 2-2 Programmer’s Model 3-1 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.
Contents Open Access 4 5 Contents-ii ARM Instruction Set 4-1 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.
Contents 6 7 8 Format 18: unconditional branch Format 19: long branch with link Instruction Set Examples Memory Interface 6-1 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6-2 6-2 6-4 6-9 6-10 6-12 6-12 6-12 6-13 6-15 Overview Cycle Types Address Timing Data Transfer Size Instruction Fetch Memory Management Locked Operations Stretching Access Times The ARM Data Bus The External Data Bus Coprocessor Interface 7-1 7.1 7.2 7.3 7.4 7.5 7.
Contents 9 Open Access 10 11 ICEBreaker Module 9-1 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9-2 9-3 9-6 9-8 9-9 9-10 9-11 9-13 9-13 9-13 9-14 Instruction Cycle Operations 10-1 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.19 10.
Contents AC Parameters 12-1 12.1 12.
Open Access Contents Contents-vi ARM7TDMI Data Sheet ARM DDI 0029E
1 1 11 Introduction 1.1 Introduction 1-2 1.2 ARM7TDMI Architecture 1-2 1.3 ARM7TDMI Block Diagram 1-4 1.4 ARM7TDMI Core Diagram 1-5 1.5 ARM7TDMI Functional Diagram 1-6 ARM7TDMI Data Sheet ARM DDI 0029E Open Access This chapter introduces the ARM7TDMI architecture, and shows block, core, and functional diagrams for the ARM7TDMI.
Introduction 1.1 Introduction The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance for very low power consumption and price. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers.
Introduction 1.2.2 THUMB’s Advantages THUMB instructions operate with the standard ARM register configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the same effect on the processor model. The major advantage of a 32-bit (ARM) architecture over a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a large address space efficiently.
Introduction 1.
Introduction 1.
Introduction 1.
1 2 11 Signal Description 2.1 Signal Description ARM7TDMI Data Sheet ARM DDI 0029E Open Access This chapter lists and describes the signals for the ARM7TDMI.
Signal Description 2.1 Signal Description The following table lists and describes all the signals for the ARM7TDMI. Transistor sizes For a 0.6 µm ARM7TDMI: INV4 driver has transistor sizes of p = 22.32 µm/0.6 µm N = 12.6 µm/0.6 µm INV8 driver has transistor sizes of p = 44.64 µm/0.6 µm N = 25.2 µm/0.
Name Type Description APE Address pipeline enable. IC When HIGH, this signal enables the address timing pipeline. In this state, the address bus plus MAS[1:0], nRW, nTRANS, LOCK and nOPC change in the phase 2 prior to the memory cycle to which they refer. When APE is LOW, these signals change in the phase 1 of the actual cycle. Please refer to ➲ Chapter 6, Memory Interface for details of this timing. BIGEND Big Endian configuration.
Open Access Signal Description Name Type Description COMMTX Communications Channel Transmit O When HIGH, this signal denotes that the comms channel transmit buffer is empty. This signal changes on the rising edge of MCLK. See ➲9.11 Debug Communications Channel on page 9-14 for more information on the debug comms channel. CPA Coprocessor absent. IC A coprocessor which is capable of performing the operation that ARM7TDMI is requesting (by asserting nCPI) should take CPA LOW immediately.
Name Type Description DBGRQI Internal debug request 04 This signal represents the debug request signal which is presented to the processor. This is the combination of external DBGRQ, as presented to the ARM7TDMI macrocell, and bit 1 of the debug control register. Thus there are two conditions where this signal can change. Firstly, when DBGRQ changes, DBGRQI will change after a propagation delay.
Open Access Signal Description Name Type Description EXTERN1 External input 1. IC This is an input to the ICEBreaker logic in the ARM7TDMI which allows breakpoints and/or watchpoints to be dependent on an external condition. HIGHZ 04 This signal denotes that the HIGHZ instruction has been loaded into the TAP controller. See ➲ Chapter 8, Debug Interface for details.
Name Type Description MCLK Memory clock input. IC This clock times all ARM7TDMI memory accesses and internal operations. The clock has two distinct phases - phase 1 in which MCLK is LOW and phase 2 in which MCLK (and nWAIT) is HIGH. The clock may be stretched indefinitely in either phase to allow access to slow peripherals or memory. Alternatively, the nWAIT input may be used with a free running MCLK to achieve the same effect. nCPI Not Coprocessor instruction.
Open Access Signal Description Name Type Description nMREQ Not memory request. 04 This signal, when LOW, indicates that the processor requires memory access during the following cycle. The signal becomes valid during phase 1, remaining valid through phase 2 of the cycle preceding that to which it refers. nOPC Not op-code fetch. 08 When LOW this signal indicates that the processor is fetching an instruction from memory; when HIGH, data (if present) is being transferred.
Name Type Description nWAIT Not wait. IC When accessing slow peripherals, ARM7TDMI can be made to wait for an integer number of MCLK cycles by driving nWAIT LOW. Internally, nWAIT is ANDed with MCLK and must only change when MCLK is LOW. If nWAIT is not used it must be tied HIGH. PCLKBS Boundary scan update clock 04 This is a TCK2 wide pulse generated when the TAP controller state machine is in the UPDATE-DR state and scan chain 3 is selected.
Open Access Signal Description Name Type Description SHCLKBS Boundary scan shift clock, phase 1 04 This control signal is provided to ease the connection of an external boundary scan chain. SHCLKBS is used to clock the master half of the external scan cells. When in the SHIFT-DR state of the state machine and scan chain 3 is selected, SHCLKBS follows TCK1. When not in the SHIFT-DR state or when scan chain 3 is not selected, this clock is LOW.
Signal Description Name Type Description VDD Power supply. P These connections provide power to the device. VSS Ground. P These connections are the ground reference for all signals.
Open Access Signal Description 2-12 ARM7TDMI Data Sheet ARM DDI 0029E
1 3 11 Programmer’s Model 3.1 Processor Operating States 3-2 3.2 Switching State 3-2 3.3 Memory Formats 3-2 3.4 Instruction Length 3-3 3.5 Data Types 3-3 3.6 Operating Modes 3-4 3.7 Registers 3-4 3.8 The Program Status Registers 3-8 3.9 Exceptions 3-10 3.11 Reset 3-15 ARM7TDMI Data Sheet ARM DDI 0029E Open Access This chapter describes the two operating states of the ARM7TDMI.
Programmer’s Model 3.1 Processor Operating States From the programmer’s point of view, the ARM7TDMI can be in one of two states: Note 3.2 ARM state which executes 32-bit, word-aligned ARM instructions. THUMB state which operates with 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit 1 to select between alternate halfwords. Transition between these two states does not affect the processor mode or the contents of the registers.
Programmer’s Model 3.3.1 Big endian format In Big Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24.
Programmer’s Model 3.
Programmer’s Model FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.
Programmer’s Model 3.7.2 The THUMB state register set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. This is shown in ➲Figure 3-4: Register organization in THUMB state.
Programmer’s Model • THUMB state LR maps onto ARM state R14 • The THUMB state Program Counter maps onto the ARM state Program Counter (R15) This relationship is shown in ➲Figure 3-5: Mapping of THUMB state registers onto ARM state registers.
Programmer’s Model 3.8 The Program Status Registers The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. These registers • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operating mode The arrangement of bits is shown in ➲Figure 3-6: Program status register format.
Interrupt disable bits The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively. The mode bits The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor’s operating mode, as shown in ➲Table 3-1: PSR mode bit values on page 3-9. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used.
Programmer’s Model 3.9 Exceptions Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order - see ➲3.9.10 Exception priorities on page 3-14. 3.9.
Programmer’s Model 3.9.3 Exception entry/exit summary ➲Table 3-2: Exception entry/exit summarises the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler.
Programmer’s Model FIQ may be disabled by setting the CPSR’s F flag (but note that this is not possible from User mode). If the F flag is clear, ARM7TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction. 3.9.5 IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered.
Programmer’s Model After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or Thumb): SUBS PC,R14_abt,#4 for a prefetch abort, or SUBS PC,R14_abt,#8 for a data abort This restores both the PC and the CPSR, and retries the aborted instruction. 3.9.7 Software interrupt The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function.
Programmer’s Model 3.9.10 Exception priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1 Reset 2 Data abort 3 FIQ 4 IRQ 5 Prefetch abort Lowest priority: 6 Undefined Instruction, Software interrupt.
Programmer’s Model 3.11 Reset When the nRESET signal goes LOW, ARM7TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. When nRESET goes HIGH again, ARM7TDMI: Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined. 2 Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR’s T bit.
Open Access Programmer’s Model 3-16 ARM7TDMI Data Sheet ARM DDI 0029E
