User guide

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ARM DUI 0224I

RealView Platform Baseboard for

ARM926EJ-S

™

HBI-0117

User Guide

Summary of content (402 pages)

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RealView Platform Baseboard for ARM926EJ-S User Guide Copyright © 2003-2010 ARM Limited. All rights reserved. Release Information Change History Date Issue Confidentiality Change November 2003 A Non-Confidential First release. April 2004 B Non-Confidential Second release. Added configuration details for USB debug, PCI, and Boot Monitor. November 2005 C Non-Confidential Third release. Corrected reported defects and added requested enhancements.
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Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Product Status The information in this document is final, that is for a developed product. Web Address http://www.arm.com ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Conformance Notices This section contains conformance notices. Federal Communications Commission Notice This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c). CE Declaration of Conformity The system should be powered down when not in use. The PB926EJ-S generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications.
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Contents RealView Platform Baseboard for ARM926EJ-S User Guide Preface About this manual ...................................................................................... xviii Feedback .................................................................................................... xxv Chapter 1 Introduction 1.1 1.2 1.3 Chapter 2 Getting Started 2.1 2.2 2.3 2.4 2.5 2.6 Chapter 3 Setting up the RealView Platform ...............................................................
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Contents 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 Chapter 4 3-22 3-33 3-35 3-56 3-59 3-61 3-65 3-68 3-71 3-72 3-74 3-75 3-79 3-80 3-81 3-84 3-87 3-88 3-92 3-94 Programmer’s Reference 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 vi Reset controller ........................................................................................ Power supply control .........................
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Contents 4.26 4.27 4.28 Appendix A Signal Descriptions A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13 Appendix B About memory expansion ........................................................................... E-2 Fitting a memory board ............................................................................... E-5 EEPROM contents ...................................................................................... E-6 Connector pinout ...................................................
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Contents F.3 Appendix G Configuring the USB Debug Connection G.1 G.2 G.3 G.4 viii Header connectors ..................................................................................... F-4 Installing the RealView ICE Micro Edition driver ........................................ G-2 Changes to RealView Debugger ................................................................ G-5 Using the USB debug port to connect RealView Debugger .......................
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List of Tables RealView Platform Baseboard for ARM926EJ-S User Guide Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 ARM DUI 0224I Change History ............................................................................................................. ii Selecting the boot device ....................................................................
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List of Tables Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 3-20 Table 3-21 Table 3-22 Table 3-23 Table 3-24 Table 3-25 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 4-11 Table 4-12 Table 4-13 Table 4-14 Table 4-15 Table 4-16 Table 4-17 Table 4-18 Table 4-19 Table 4-20 Table 4-21 Table 4-22 Table 4-23 Table 4-24 Table 4-25 Table 4-26 Table 4-27 Table 4-28 Table 4-29 Table 4-30 Table 4-31 Table 4-32 Table 4-33 Table 4-34
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List of Tables Table 4-36 Table 4-37 Table 4-38 Table 4-39 Table 4-40 Table 4-41 Table 4-42 Table 4-43 Table 4-44 Table 4-45 Table 4-46 Table 4-47 Table 4-48 Table 4-49 Table 4-50 Table 4-51 Table 4-52 Table 4-53 Table 4-54 Table 4-55 Table 4-56 Table 4-57 Table 4-58 Table 4-59 Table 4-60 Table 4-61 Table 4-62 Table 4-63 Table 4-64 Table 4-65 Table 4-66 Table 4-67 Table 4-68 Table 4-69 Table 4-70 Table 4-71 Table 4-72 Table 4-73 Table 4-74 Table 4-75 Table 4-76 Table 4-77 Table A-1 Table A-2 Table A-3 Tabl
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List of Tables Table A-6 Table A-7 Table A-8 Table A-9 Table A-10 Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 Table B-1 Table B-2 Table B-3 Table B-4 Table B-5 Table B-6 Table B-7 Table C-1 Table C-2 Table C-3 Table C-4 Table C-5 Table C-6 Table C-7 Table C-8 Table D-1 Table D-2 Table D-3 Table D-4 Table D-5 Table D-6 Table E-1 Table E-2 Table E-3 Table E-4 Table E-5 Table E-6 Table F-1 Table G-1 Table G-2 xii CLCD Interface board connector J18 ......................................
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List of Figures RealView Platform Baseboard for ARM926EJ-S User Guide Figure 1-1 Figure 1-2 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 ARM DUI 0224I Key to timing diagram conventions ............................................................................. xx PB926EJ-S layout ......................................................................
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List of Figures Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 3-21 Figure 3-22 Figure 3-23 Figure 3-24 Figure 3-25 Figure 3-26 Figure 3-27 Figure 3-28 Figure 3-29 Figure 3-30 Figure 3-31 Figure 3-32 Figure 3-33 Figure 3-34 Figure 3-35 Figure 3-36 Figure 3-37 Figure 3-38 Figure 3-39 Figure 3-40 Figure 3-41 Figure 3-42 Figure 3-43 Figure 3-44 Figure 3-45 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9
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List of Figures Figure 4-15 Figure 4-16 Figure 4-17 Figure 4-18 Figure 4-19 Figure 4-20 Figure 4-21 Figure 4-22 Figure 4-23 Figure 4-24 Figure 4-25 Figure 4-26 Figure 4-27 Figure 4-28 Figure 4-29 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure A-10 Figure A-11 Figure A-12 Figure A-13 Figure A-14 Figure A-15 Figure A-16 Figure A-17 Figure A-18 Figure A-19 Figure B-1 Figure C-1 Figure C-2 Figure C-3 Figure C-4 Figure C-5 Figure C-6 Figure C-7 Figure C
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List of Figures Figure D-4 Figure D-5 Figure D-6 Figure E-1 Figure E-2 Figure E-3 Figure E-4 Figure E-5 Figure E-6 Figure E-7 Figure F-1 Figure F-2 Figure F-3 Figure F-4 Figure F-5 Figure F-6 Figure G-1 Figure G-2 Figure G-3 Figure G-4 Figure G-5 Figure G-6 Figure G-7 Figure G-8 xvi JTAG signal flow on the PCI backplane ................................................................... D-9 AMP Mictor connector J4 ........................................................................................
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Preface This preface introduces the RealView Platform Baseboard for ARM926EJ-S User Guide. It contains the following sections: • About this manual on page xviii • Feedback on page xxv. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Preface About this manual This document describes how to set up and use the RealView Platform Baseboard for the ARM926EJ-S (PB926EJ-S). Product revision status The rnpn identifier indicates the revision status of the product described in this manual, where: rn Identifies the major revision of the product. pn Identifies the minor revision or modification status of the product.
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Preface Appendix A Signal Descriptions Refer to this appendix for a description of the signals on the connectors. Appendix B Specifications Refer to this appendix for electrical, timing, and mechanical specifications. Appendix C CLCD Display and Adaptor Board Refer to this appendix for details of the CLCD display and interface. Appendix D PCI Backplane and Enclosure Refer to this appendix for details of the PCI backplane board.
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Preface monospace Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. monospace Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value. monospace bold Denotes language keywords when used outside example code.
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Preface Signals The signal conventions are: Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means HIGH for active-HIGH signals and LOW for active-LOW signals. Lower-case n Denotes an active-LOW signal. Prefix A Denotes global Advanced eXtensible Interface (AXI) signals: Prefix AR Denotes AXI read address channel signals. Prefix AW Denotes AXI write address channel signals. Prefix B Denotes AXI write response channel signals.
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Preface Further reading This section lists publications by ARM Limited, and by third parties. ARM Limited periodically provides updates and corrections to its documentation. See http://www.arm.com for current errata sheets, addenda, and the Frequently Asked Questions list. ARM publications This manual contains information that is specific to the PB926EJ-S Platform Baseboard.
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Preface The following publications provide information about ARM PrimeCell® and other peripheral or controller devices: • ARM PrimeCell Advanced Audio CODEC Interface (PL041) Technical Reference Manual (ARM DDI 0173) • ARM PrimeCell Color LCD Controller (PL110) Technical Reference Manual (ARM DDI 0161) • ARM PrimeCell DMA (PL080) Technical Reference Manual (ARM DDI 0196) • ARM Dual-Timer Module (SP804) Technical Reference Manual (ARM DDI 0271) • ARM PrimeCell GPIO (PL061) Technical Reference Manual (ARM DD
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Preface Other publications This section lists relevant documents published by third parties: The following publication describes the JTAG ports with which Multi-ICE or RealView ICE communicates: • IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1). The following datasheets describe some of the integrated circuits or modules used on the PB926EJ-S: xxiv • CODEC with Sample Rate Conversion and 3D Sound (LM4549) National Semiconductor, Santa Clara, CA.
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Preface Feedback ARM® Limited welcomes feedback both on the PB926EJ-S and on the documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanation of your comments. Feedback on this manual If you have any comments about this document, send email to errata@arm.com giving: • the title • the number • the relevant page number(s) to which your comments apply • a concise explanation of your comments.
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Chapter 1 Introduction This chapter introduces the PB926EJ-S. It contains the following sections: • About the PB926EJ-S on page 1-2 • PB926EJ-S architecture on page 1-4 • Precautions on page 1-9. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Introduction 1.1 About the PB926EJ-S The PB926EJ-S provides a development system that you can use to develop products around the ARM926EJ-S PXP Development Chip. You can use the PB926EJ-S as a basic development system with a power supply and a connection to a JTAG interface unit.
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Introduction S1 configuration switches Mouse OTG USB USB 0 (top) 1 (bottom) UART 0 (top) 1 (bottom) UART 2 (top) 3 (bottom) CLCD expansion connector Line out (top) Line in (bottom) 2X16 character LCD GP PUSH (green LED) Mic in RESET (orange LED) FPGA debug DEV CHIP CONFIG (blue LED) MMC 0 (top) 1 (bottom) FPGA CONFIG (yellow LED) Smart card 0 (top) 1 (bottom) JTAG Trace port Logic Tile expansion 0 CFGEN LED (orange) 1 0 S6 GP (user) switches CONFIG link Standby/ power GP (user) LEDs
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Introduction 1.2 PB926EJ-S architecture The major components on the platform are: • ARM926EJ-S PXP Development Chip equipped with: — ARM926EJ-S processor that supports 32-bit ARM and 16-bit Thumb instructions sets and includes features for direct execution of Java byte codes.
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Introduction • • • • • • • • • • • • • • • ARM DUI 0224I Field Programmable Gate-Array (FPGA) that implements: — SSP, Smart Card, two MMC/SD card, UART, and two KMI controllers — configuration registers — interface to onboard Ethernet controllers — interface to onboard audio CODEC — interface to onboard On-the-Go (OTG) USB controller (three connectors) — registers for status, ID, onboard switches, LEDs, and clock control — a secondary interrupt controller and external DMA control logic — interface to PC
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Introduction 1.2.1 System architecture Figure 1-2 shows the architecture of the PB926EJ-S. CLCD expansion connector PB926EJ-S VGA DAC and PAL ARM926EJ-S Dev.
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Introduction 1.2.2 ARM926EJ-S PXP Development Chip For details on the ARM926EJ-S PXP Development Chip, see ARM926EJ-S PXP Development Chip on page 3-3 and the ARM926EJ-S PXP Development Chip Reference Manual. 1.2.3 PB926EJ-S FPGA The FPGA provides system control and configuration functions for the PB926EJ-S that enable it to operate as a standalone development system or with expansion RealView Logic Tiles or PCI cards. See FPGA on page 3-17.
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Introduction 1.2.6 Memory The volatile memory system includes SSRAM and SDRAM memory. You can expand this memory by installing external static or dynamic memory expansion boards. The nonvolatile memory system consists of 128MB of 32-bit flash. The flash is managed by the static memory controller in the ARM926EJ-S PXP Development Chip. You can expand the flash memory by installing an external static memory expansion board. See Appendix E Memory Expansion Boards. 1.2.
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Introduction 1.3 Precautions This section contains safety information and advice on how to avoid damage to the PB926EJ-S. 1.3.1 Ensuring safety The PB926EJ-S can be powered from one of the following sources: • the supplied power supply connected to J35 • a bench power supply connected to the screw terminals on header J34 • an external PCI bus. Warning Do not supply more than one power source. If you are using the baseboard with the PCI enclosure for example, do not connect a power source to J35 or J34.
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Chapter 2 Getting Started This chapter describes how to set up and prepare the PB926EJ-S for use. It contains the following sections: • Setting up the RealView Platform on page 2-2 • Setting the configuration switches on page 2-3 • Connecting JTAG debugging equipment on page 2-8 • Connecting the Trace Port Analyzer on page 2-10 • Supplying power on page 2-13 • Using the PB926EJ-S Boot Monitor and platform library on page 2-14. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Getting Started 2.1 Setting up the RealView Platform The following items are supplied with the PB926EJ-S: • the PB926EJ-S printed-circuit board mounted on a metal tray • an AC power supply that provides a 12VDC output • a CD containing sample programs, Boot Monitor code, FPGA and PLD images, and additional documentation • this user guide. To set up the PB926EJ-S as a standalone development system: 1.
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Getting Started 2.2 Setting the configuration switches Configuration switches S1 and S6, shown in Figure 2-1, control how the PB926EJ-S configures itself and the action to take after reset. Figure 2-1 Location of S1-1 and S6-1 2.2.1 Boot memory configuration The configuration switches S1-1 to S1-8 determine boot memory type, the FPGA image, and the Logic Tile image, memory configuration, and FPGA options at power on. Use switch S1-1 and S1-2 to select the boot device as shown in Table 2-1 on page 2-4.
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Getting Started Table 2-1 Selecting the boot device S1-2 S1-1 Device OFF OFF Reserved (boot from NOR flash 2 - default setting) OFF ON NOR flash 1, see Booting from NOR flash 1 on page 4-12 ON OFF Reserved ON ON AHB expansion memory, see Booting from AHB expansion memory on page 4-14 Configuration switches S1-1 to S1-8 are not normally changed from their factory default positions listed in Table 2-2. For more information on configuration switch S1, see Configuration control on page 3-7.
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Getting Started 2.2.2 LED indicators Table 2-3 lists the PB926EJ-S LED indicators and their function. Table 2-3 LED Indicators ARM DUI 0224I LED ID Color Device Function 5V OK Green D29 Indicates that the 5V power supply is on 3V3 OK Green D34 Indicates that the 3V3 power supply is on Standby Red D39 Indicates that the PB926EJ-S is in standby mode and the power is off.
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Getting Started Table 2-3 LED Indicators (continued) 2-6 LED ID Color Device Function Local Done Green D7 Indicates that the PB926EJ-S FPGA device has been configured USB Debug Busy Amber D22 Indicates that the embedded Real View ICE Micro Edition hardware is active USB Debug On Green D23 Indicates that the embedded RealView ICE Micro Edition hardware is enabled Copyright © 2003-2010 ARM Limited. All rights reserved.
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Getting Started 2.2.3 Boot Monitor configuration Switches S6-1 and S6-3 control the Boot Monitor. The setting of S6-1 determines whether the Boot Monitor starts after a reset: S6-1 OFF A prompt is displayed enabling you to enter Boot Monitor commands. S6-1 ON The Boot Monitor executes a boot script that has been loaded into flash. The boot script can execute any Boot Monitor commands. It typically selects and runs an image in application flash.
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Getting Started 2.3 Connecting JTAG debugging equipment You can use JTAG debugging equipment and the JTAG connector, or the USB debug port, to: • connect a debugger to the ARM926EJ-S core and download programs to memory and debug them • program new configuration images into the configuration flash, FPGA, and PLDs on the board. (You cannot program the normal flash from configuration mode.) The setup for using a JTAG interface with the PB926EJ-S is shown in Figure 2-2.
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Getting Started Figure 2-3 USB debug port connection Note For more details on JTAG debugging and selection between the JTAG and USB debug connector, see JTAG and USB debug port support on page 3-96. If you are using the ARM RealView® Debugger, see Appendix G Configuring the USB Debug Connection for installation and configuration details. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Getting Started 2.4 Connecting the Trace Port Analyzer The ARM926EJ-S PXP Development Chip incorporates an ARM9 Embedded Trace Macrocell (ETM9). This enables you to carry out real-time debugging by connecting external trace equipment to the PB926EJ-S. The ETM9 monitors the program execution and sends a compressed trace to the Trace Port Analyzer (TPA). The TPA buffers this information and transmits it to the debugger where it is decompressed and used to reconstruct the complete instruction flow.
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Getting Started Figure 2-5 Example of RealView ICE and RealView Trace Note The high-density cable from the RealView ICE box requires a buffer board to connect to the JTAG connector on the PB926EJ-S. The low-density cable can be used to connect the RealView ICE box directly to the JTAG connector, but this interface operates at lower speed. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Getting Started 2.4.1 About using trace The components used for trace capture are: ETM The Embedded Trace Macrocell is part of the ARM926EJ-S PXP Development Chip. It monitors the ARM core buses and outputs compressed information through the trace port to a trace connector. The on-chip ETM contains trigger and filter logic to control what is traced. Trace connector and adaptor board The trace connector enables you to connect a TPA to the PB926EJ-S. The connector is a high-density AMP Mictor connector.
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Getting Started 2.5 Supplying power When using the PB926EJ-S as a standalone development system, you must connect the supplied brick power supply to power socket J35 or an external bench power supply to the screw-terminal connector. See Figure 2-6. Figure 2-6 Power connectors Note If you are using the supplied brick power supply connected to J35, the Standby/power pushbutton toggles the power on and off.
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Getting Started 2.6 Using the PB926EJ-S Boot Monitor and platform library The PB926EJ-S Boot Monitor is a collection of tools and utilities designed as an aid to developing applications on thePB926EJ-S.
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Getting Started Table 2-4 lists the commands for the Boot Monitor. Table 2-4 Boot Monitor commands Command Action @ script_file Runs a script file. ALIAS alias commands Create an alias command alias for the string of commands contained in commands. CLEAR BOOTSCRIPT Clear the current boot script. The Boot Monitor will prompt for input on reset even if the S6-1 is set to ON to indicate that a boot script should be run. CONFIGURE Enter Configure subsystem.
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Getting Started Table 2-5 Boot Monitor Configure commands Command Action DISPLAY DATE Display date. DISPLAY HARDWARE Display hardware information (for example, the FPGA revisions). DISPLAY TIME Display time. EXIT Exit the configure commands and return to executing standard Boot Monitor commands. HELP List the configure commands. QUIT Alias for EXIT. Exit the Configure commands and return to standard Boot Monitor commands. SET DATE dd/mm/yy Set date.
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Getting Started Table 2-6 Boot Monitor Debug commands (continued) Command Action QUIT Alias for EXIT. Exit the Debug commands and return to standard Boot Monitor commands. START TIMER Start a timer. STOP TIMER Stop the timer started with the START TIMER command and display the elapsed time. Table 2-7 lists the commands for the NOR Flash subsystem. Table 2-7 Boot Monitor NOR flash commands Command Action DISPLAY IMAGE name Displays details of image name.
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Getting Started Table 2-7 Boot Monitor NOR flash commands (continued) Command Action UNRESERVE SPACE address Free the space starting at address in NOR flash. This space can be used by the Boot Monitor. WRITE BINARY file [NAME new_name] [FLASH_ADDRESS address] [LOAD_ADDRESS address] [ENTRY_POINT address] Write a binary file to flash. By default, the image is identified by its file name. Use NAME new_name to specify a name instead of using the default name.
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Getting Started • VFP=1/0, defines VFP support (Default 0, no VFP support). Note The image must be build as a simple image. Scatter loading is not supported. The build options define the subdirectory in the Builds directory that contains the compile and link output: ___Endian + further component specific options For example, Release_ARM_Little_Endian or Debug_Thumb_Big_Endian_NoDiskOnChip.
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Getting Started 2.6.3 Loading Boot Monitor into NOR flash If the flash becomes corrupt and the board no longer runs the Boot Monitor, the Boot Monitor must be reprogrammed into flash. Note The Boot Monitor is normally located in NOR flash 2 instead of NOR flash 1. You can, however, load the Boot Monitor into NOR flash 1 instead of NOR flash 2 if this is requiredfor a specific application. Because the debugger does not initialize SDRAM, the Boot Monitor image cannot be loaded and run directly.
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Getting Started where path is the directory (C:\temp for example) that contains the boot monitor image. • To load the image to NOR flash 1, at the Boot Monitor prompt enter: >FLASH Flash> WRITE IMAGE path\Boot_Monitor.axf NAME boot_monitor FLASH_ADDRESS 0x34000000 where path is the directory (C:\temp for example) that contains the boot monitor image. Note Very long path names can cause problems with semihosting. To avoid this, move the image to a temporary directory. 9.
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Getting Started Supported devices for character output are: • :UART-0 (default destination if debugger is not capturing semihosting calls) • :UART-1 • :UART-2 • :UART-3 • :CHARLCD. The STDIO calls are redirected within retarget.c. Redirection depends on the setting of switch S6-3, see Boot Monitor configuration on page 2-7. 2.6.5 Rebuilding the platform library All firmware components are built using GNUmake, which is available for UNIX, Linux and for most Windows versions.
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Getting Started 2.6.6 Building an application with the platform library The platform library on the CD provides all required initialization code to bring the PB926EJ-S up from reset. The library is used by the Boot Monitor, but it can be used by an application independently of the other code in the Boot Monitor. The platform library supports: • remapping of boot memory • SDRAM initialization • UARTs • Time-of-Year clock • output to the character LCD display • C library system calls.
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Getting Started 2.6.7 Loading and running an application from NOR flash To run an image from NOR flash: 1. Build the application as described in Building an application with the platform library on page 2-23 and specify a link address suitable for flash. There are the following options for selecting the address: Load region in flash The image is linked such that its load region, though not necessarily its execution region, is in flash.
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Getting Started 3. The command used to program the image depends on the type of image: • To program the ELF image into flash, use the following command line: flash> WRITE IMAGE elf_file_name NAME name FLASH_ADDRESS address The entry point and load address for ELF images are taken from the image itself.
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Chapter 3 Hardware Description This chapter describes the on-board hardware.
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Hardware Description • • • • • 3-2 Synchronous Serial Port, SSP on page 3-84 User switches and LEDs on page 3-87 USB interface on page 3-92 UART interface on page 3-88 Test, configuration, and debug interfaces on page 3-94. Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description 3.
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Hardware Description The ARM926EJ-S PXP Development Chip incorporates the following features: ARM926EJ-S The ARM926EJ-S CPU is a member of the ARM9 Thumb® family. The ARM926EJ-S (r0p3) macrocell is a 32-bit cached processor with ARMv5TE architecture that supports the ARM and Thumb instruction sets and includes features for direct execution of Java byte codes. Executing Java byte codes requires the Java Technology Enabling Kit (JTEK).
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Hardware Description There are also two expansion master buses (AHB M1 and AHB M2) and one expansion slave bus (AHB S). The expansion bus bridges are configurable to support different performance and complexity trade-offs. A bus matrix inside the ARM926EJ-S PXP Development Chip manages the multiple paths between each master and the peripherals and memory. The AHB Monitor provides information on bus accesses that can be recorded by an attached logic analyzer.
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Hardware Description Timers There are four 32-bit down counters that can be used to generate interrupts at programmable intervals. A Real-Time-Clock is fed with an external 1Hz signal. Synchronous serial port The SSP provides a master or slave interface for synchronous serial communications using Motorola SPI, TI, or National Semiconductor Microwire devices.
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Hardware Description Configuration switches The S1 boot option select switches are listed in Table 3-1. For more information on setting boot memory options, see Setting the configuration switches on page 2-3 and Configuration and initialization on page 4-9, and Boot Select Register, SYS_BOOTCS on page 4-34. Switch S1 values determine the BOOTCSSEL[7:0] signals. (S1-1 controls BOOTCSSEL0 and S1-8 controls BOOTCSSEL7.
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Hardware Description Configuration from the DEV CHIP RECONFIG pushbutton FPGA registers SYS_CFGDATA1 and SYS_CFGDATA2 contain configuration data that is applied to the ARM926EJ-S PXP Development Chip when the DEV CHIP RECONFIG pushbutton is pressed. When nPBSDCREFCONFIG is asserted, the configuration values stored in the FPGA configuration registers are output to the development chip data bus (HDATAM1 and HDATAM2) pins.
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Hardware Description The configuration block in the development chip samples the state of the HDATAMx pins while the rest of the chip is held in reset. The state of these pins is stored and used to drive configuration signals within the chip and to define the operating mode of the chip when reset is released. For more detail on the configuration signals, see Configuration registers SYS_CFGDATAx on page 4-25 and the ARM926EJ-S Development Chip Reference Manual.
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Hardware Description External masters drive the ARM926EJ-S PXP Development Chip AHB S port which goes through an AHB-AHB bridge to the expansion master port on the matrix. This master can access most of the slaves within the ARM926EJ-S PXP Development Chip, including the GX175 MPMC (SDRAM controller), the PL093 SSMC (static memory controller), and the expansion slaves. External slaves are connected to the ARM926EJ-S PXP Development Chip AHB M1 and AHB M2 ports.
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Hardware Description Figure 3-3 Example of multiple masters The default memory map for each of the internal buses is slightly different as shown in Figure 3-4 on page 3-13 and Figure 3-5 on page 3-14. Caution The AHB S bus is driven by the PCI bridge in the FPGA or by an external Logic Tile. Do not use the FPGA PCI master to AHB S bus path to drive the PCI M2 addresses at 0x41000000–0x6FFFFFFF.
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Hardware Description 3.1.4 Memory interface Memory access is provided by a MultiPort Memory Controller (MPMC) and a Static Memory Controller (SSMC) located in the ARM926EJ-S PXP Development Chip. One or two expansion memory boards can be added to increase the amount of flash, SRAM, and SDRAM memory. Memory (or memory-mapped peripherals) can also be accessed on an optional Logic Tile or PCI card.
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Hardware Description 3.1.5 AHB monitor The ARM926EJ-S PXP Development Chip contains a multi-layer AHB system to provide high bandwidth connectivity between the various bus masters and slaves both within and outside the ARM926EJ-S PXP Development Chip. The AHB layer monitors observe the activity on their respective bus signals to produce real-time information that is exported off-chip to a logic analyzer. The AHB monitor also contains event counters that monitor bus transactions.
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Hardware Description 3.2 FPGA Figure 3-8 shows the architecture of the FPGA on the PB926EJ-S. Figure 3-8 FPGA block diagram ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description For details on FPGA components, see: • FPGA configuration • Reset controller on page 3-22 • Clock architecture on page 3-35 • Advanced Audio Codec Interface, AACI on page 3-56 • Character LCD controller on page 3-59 • Ethernet interface on page 3-68 • Keyboard/Mouse Interface, KMI on page 3-74 • Memory Card Interface, MCI on page 3-75 • PCI interface on page 3-79 • Smart Card interface, SCI on page 3-81 • User switches and LEDs on page 3-87 • UART interface on page 3-88 • USB interface
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Hardware Description Figure 3-9 FPGA configuration Table 3-2 FPGA image selection S1-7 S1-6 FPGA image image Addressa OFF OFF FPGA image 1 (this is the image supplied with the board) 0x0 OFF ON FPGA image 2 (this image is not supplied with the board) 0x200000 ON OFF FPGA image 3 (this image is not supplied with the board) 0x400000 ON ON FPGA image 4 (this image is not supplied with the board) 0x600000 a.
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Hardware Description nTRST LOCAL_DONE GLOBAL_DONE nSYSPOR 2.6μs 7μs Released by Logic Tiles Figure 3-10 FPGA reload sequence Note The configuration flash can hold four FPGA images. However, only one FPGA image is provided. The configuration flash is a separate device and not part of the user flash. You can use a JTAG debugger or the Progcards utility to reprogram the PLDs, FPGA, and flash if the PB926EJ-S is placed in configuration mode. See also JTAG and USB debug port support on page 3-96.
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Hardware Description If autoconfiguration fails, load the configuration file (.cfg) for the board. For details on manual configuration, see the readme.txt file on the CD. 4. Run the Progcards utility from: install_directory\Versatile\PB926EJS\build\Release\boardfiles\ 5. Choose the required image for the configuration PLD. Caution The 1.5V cell battery provides the VBATT backup voltage to the external DS1338 time-of-year clock and FPGA encryption key circuitry within the FPGA.
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Hardware Description 3.3 Reset controller The reset controller initializes the ARM926EJ-S PXP Development Chip, the FPGA, and external controllers as a result of a reset. The PB926EJ-S can be reset from the following sources: • power failure • reset button • PCI backplane • Logic Tiles • JTAG • software.
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Hardware Description 3.3.2 Reset level Table 3-3 lists the default levels of reset that results from external sources. Table 3-3 Reset sources and effects FPGA reloaded and Dev. Chip configured with default values Dev.
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Hardware Description Figure 3-12 Reset signal sequence A state machine in the FPGA (see Figure 3-13 on page 3-26) uses the value of SYS_RESETCTL and the external reset signals to sequence the reset signals (see also, Reset Control Register, SYS_RESETCTL on page 4-31). ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description 3.3.3 Memory aliasing at reset Under normal operation, the PB926EJ-S has dynamic memory located at 0x0. In order to load the boot code however, non-volatile memory must be remapped to the boot address. Remapping the memory is done by changing how the chip select signals in the ARM926EJ-S PXP Development Chip connect to the external chip select signals that control memory devices.
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Hardware Description 3.3.4 Reset signals Table 3-4 describes reset signals. Table 3-4 Reset signal descriptions Name Function AACIRESET System reset to audio CODEC. APPLYCFGWORD This internal signal causes the FPGA to apply configuration data from the SYS_CFGDATAx registers in the FPGA to the M1 and M2 data buses, see Configuration registers SYS_CFGDATAx on page 4-25. nBOARDPOR This signal resets the configuration PLD and configuration flash.
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Hardware Description Table 3-4 Reset signal descriptions (continued) Name Function nPBRESET Push-button reset signal to the FPGA. The signal is generated by pressing the reset button. nPBSDCRECONFIG This signal is generated from the DEV CHIP CONFIG pushbutton and causes a reconfiguration of the ARM926EJ-S PXP Development Chip. nPLLRESET Reset for ARM926EJ-S PXP Development Chip PLL clock circuit. nPORESET Power-on reset to development chip, configuration flash, and expansion memory.
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Hardware Description Table 3-4 Reset signal descriptions (continued) Name Function nRESET Reset signal to the development chip and FPGA. The CPU core, all system peripherals, and some system controller registers are reset. This signal is synchronized with the system bus clock to provide AMBA compliance. For details on system registers reset at different reset levels, see Table 4-4 on page 4-18.
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Hardware Description 3.3.5 Reset timing Figure 3-15 shows the power-on reset sequence. nBOARDPOR is generated at power-up and distributed to the memory expansion boards and to the FPGA configuration PLD. It also causes the assertion of the nTRST signal guarantee the embedded ICE macrocell is reset in the ARM926EJ-S PXP Development Chip. Figure 3-15 Power-on reset and configuration timing Note The release time for GLOBAL_DONE depends on any Logic Tiles in the system.
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Hardware Description 3.4 Power supply control If the PB926EJ-S is powered from the brick power supply, a nominal 12V level (VSMP) is supplied to the 5V and 3V regulators. If VSMP, drops too low, shutdown signals nPOWERFAIL, nSHDN1, and nSHDN2 become active and power is switched off. The shutdown circuitry is shown in Figure 3-16 on page 3-34. The power supply can be toggled on and off by pressing the Power/Standby pushbutton.
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Hardware Description 3.5 Clock architecture The clock domains for the PB926EJ-S are shown in Figure 3-17. Figure 3-17 Clock architecture ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description The clock domains for the PB926EJ-S are: ARM926EJ-S PXP Development Chip The ARM926EJ-S PXP Development Chip CPU clock is normally a multiplied version of GLOBALCLK that is based on OSC0. Alternatively, the CPU can be clocked from a 32kHz clock or OSC2 to test low-power operating modes. There are three external AHB bridges on the chip. These normally operate in synchronous mode and the bridge clocks are based on the CPU clock.
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Hardware Description RTC There is an external real-time clock clocked by a dedicated 32kHz crystal oscillator. The RTC outputs the 32kHz clock to the FPGA where it is buffered and then sent to the ARM926EJ-S PXP Development Chip where it can be used as the CPU clock for low-power mode. Ethernet The Ethernet controller has a 25MHz dedicated crystal oscillator for timing the Ethernet bus.
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Hardware Description The default values for clock selection and control are appropriate for most situations. You must modify the multiplexor settings if you are doing one of the following: 3-38 • Using an external Logic Tile to generate the reference clocks for the CPU or AHB bridges. • Operating one of the AHB bridges in the ARM926EJ-S PXP Development Chip in asynchronous mode with a dedicated clock input for timing the external part of the bridge. Copyright © 2003-2010 ARM Limited.
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Hardware Description 3.5.1 ARM926EJ-S PXP Development Chip clocks This section describes the clocks used by the ARM926EJ-S PXP Development Chip. Figure 3-18 shows the clock circuitry inside the chip. HCLKEXT ARM926EJ-S Dev.
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Hardware Description Table 3-5 lists the clock signals. Table 3-5 ARM926EJ-S PXP Development Chip clocks Clock signal Frequency Description Source GLOBALCLK 6–75MHz This is a master clock that is shared between the FPGA, Logic Tile, and ARM926EJ-S PXP Development Chip. ICS307 OSC0 HCLKM1 6–50MHz The AHB master interface clock is used by the AHB Bridge 1 to off-chip peripherals when it operates in asynchronous mode.
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Hardware Description Table 3-5 ARM926EJ-S PXP Development Chip clocks (continued) Clock signal Frequency Description Source Peripheral clocks 24MHz and 1MHz The SSP, SCI, and UART use an external 24MHz as reference. The timers use an external 1MHZ clock as reference. 24MHz crystal XTALCLKDRV 6–75MHz For the default clock multiplexor setting, this signal is driven from the FPGA (from OSC0) and is distributed as HCLKM1, HCLKM2, HCLKS, PLLCLKEXT, GLOBALCLK, and XTALCLKEXT.
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Hardware Description HCLKEXT (35MHz) ARM926EJ-S Dev.
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Hardware Description For the default clock source and configuration values: • OSC0 provides the XTALCLKEXT input clock for the PLL in the ARM926EJ-S PXP Development Chip. • The PLL output CPUCLK is used as the CPU core clock and as the input to the HCLK divider. • HCLK is CPUCLK divided by 1, 2, 3, or 4 depending on the value of CFGHCLKDIVSEL[1:0]. HCLK is used as the SDRAM clock MPMCCLK, and as the inputs to the MBX and SMC clock dividers.
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Hardware Description • If CPUCLK is 210MHz the total multiplier ratio of HCLKDIV and HCLKEXTDIV must be 6. • The HCLK divider is set to divide by 3 (CFGHCLKDIVSEL[1:0]=b10 ). This gives an internal AMBA bus and SDRAM clock of 70MHz. See Configuration control on page 3-7 and Memory characteristics on page 4-15. • The HCLKEXT divider must be set to divide by 2 (CFGHCLKEXTDIVSEL[2:0]=b001) so that the total divider ratio for HCLKDIV and HCLKEXTDIV is 6.
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Hardware Description Table 3-6 Asynchronous clock signals Clock signal Frequency Description Source HCLKCTRL[7:0] - These signals control the multiplexor that selects clocks for the ARM926EJ-S PXP Development Chip. FPGA HCLKM1M2F HCLKM2M2F HCLKSMF2F - These are FPGA input clocks (for M1, M2, and S) that can be routed to HCLKxM2F and used as clocks for the M1, M2, and S buses in the FPGA.
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Hardware Description Table 3-7 to Table 3-9 on page 3-48 list the source of the bridge clocks for different values of the HCLKCTRL[7:0] signals (from SYS_CONFIGDATA1[23:16]). The default value of HCLKCTRL[7:0] is 0xE0.
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Hardware Description Table 3-9 HCLKS selection HCLKCTRL signal [4] [0] [3] [7] HCLKS driven by: 1 1 X X GLOBALCLK (driven from tile, nGLOBALCLKEN pulled HIGH) 1 0 X X GLOBALCLK (driven from OSC0) 0 X 1 X HCLKSL2S and HCLKSL2F (from tile) 0 X 0 1 OSC0 (default) 0 X 0 0 OSC3 ICS307 programmable clock generators Five programmable (6–200 MHz) clocks are supplied to the FPGA by the programmable MicroClock ICS307 clock generators (OSC0–OSC4): OSCCLK0 This is the default reference cl
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Hardware Description OSCCLK2 An alternative reference clock for PLLCLKEXT. This clock can be selected as the source for CPUCLK if the ARM926EJ-S PXP Development Chip is in low-power emulation mode. This is also the alternative reference clock for the AHB M2 bridge clocks from the FPGA to the clock selection multiplexors (HCLKM2F2S, HCLKM2F2F, and HCLKM2F2L). By default, this clock is not used and the AHB M2 bridge operates in synchronous mode.
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Hardware Description where: VDW RDW DIVIDE Is the VCO divider word (4 – 511) from SYS_OSCx[8:0] Is the reference divider word (1 – 127) from SYS_OSCx[15:9] Is the divide ratio (2 to 10) selected from SYS_OSCx[18:16]: • b000 selects divide by 10 • b001 selects divide by 2 • b010 selects divide by 8 • b011 selects divide by 4 • b100 selects divide by 5 • b101 selects divide by 7 • b110 selects divide by 3 • b111 selects divide by 6.
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Hardware Description In the power-saving modes, an external low-frequency clock is used as CPUCLK. If the AHB bridges operated synchronous mode, the resulting timing for the external part of the AHB bridge would be CPUCLK divided by the values used for HCLKDIV and HCLKEXTDIV and the bus would be extremely slow. Therefore, the AHB bridges must operate in asynchronous mode and the bus timing is controlled by external clocks HCLKM1, HCLKM2, and HCLKS.
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Hardware Description 3.5.2 RealView Logic Tile clocks The PB926EJ-S can be expanded by adding RealView Logic Tiles. The HCLKCTRL[0] signal (SYS_CONFIGDATA1[16]) indicates the state of the nGLOBALCLKEN signal that selects the source for GLOBALCLK (see Table 3-10). Table 3-10 GLOBALCLK selection HCLKCTRL[0] XTALCLK/GLOBALCLK driven by: 0 XTALCLKDRV signal from FPGA (from OSC0). This is the default.
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Hardware Description 3.5.3 Peripheral clocks Table 3-11 lists the other memory and peripheral clocks on the PB926EJ-S. For more detail on the clocking system, see the files in the Schematics directory of the CD supplied with the PB926EJ-S. Table 3-11 PB926EJ-S clocks and clock control signals Clock signal Frequency Description Source AACIBITCLK 12.288MHz This is the synchronization clock from the audio CODEC. The clock is an input to the AACI PrimeCell.
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Hardware Description 3.6 Advanced Audio Codec Interface, AACI The FPGA contains an ARM PrimeCell Advanced Audio CODEC Interface (AACI) that provides communication with a CODEC using the AC-link protocol. This section provides a brief overview of the AACI. For detailed information, see PrimeCell Advanced Audio CODEC Interface (PL041) Technical Reference Manual. Note For a description of the audio CODEC signals, refer to the LM4549 datasheet available from the National Semiconductor website.
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Hardware Description Figure 3-24 Audio interface Two microphone inputs are present on J4. Only monophonic sound is supported, but microphone channel CODEC_MIC1 or CODEC_MIC2 can be selected in software. Solder link LK1 selects passive or active (electret) microphones: Link AB Active microphone with power on CODEC_MIC1 (tip). Passive microphone on CODEC_MIC2 (not powered). This is the default configuration. Link BC Active microphone with power on CODEC_MIC2 (ring).
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Hardware Description Table 3-13 AC’97 audio debug signals on J45 3-58 Pin number Signal name Description 1 AACIBITCLK Clock from the CODEC to the AACI 2 AACISYNC Frame synchronization signal from the AACI 3 AACISDATAIN Serial data from the CODEC to the AACI 4 AACI_RESET Reset signal from the AACI to the CODEC 5 AACISDATAOUT Serial data from the AACI to the CODEC 6 GND Signal ground Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description 3.7 Character LCD controller The FPGA contains a simple controller that provides an interface to a standard HD44780 16 x 2 character LCD alphanumeric display module. The character display has an 8-bit interface, DB[7:0] (CHARLCDD[7:] from the controller). The device is controlled by the E, RnW, and RS pins. The controller drives these pins with the CHARLCDE, CHARLCDnWRITE, and CHARLCDRS signals. A 3.
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Hardware Description 3.8 CLCDC interface A PrimeCell CLCD controller is present in the ARM926EJ-S PXP Development Chip. The PB926EJ-S provides a display interface with outputs to: • a VGA connector for connecting a VGA or SVGA monitor • a CLCD adaptor board with CLCD, keypad, and touchscreen connectors. (See Appendix C CLCD Display and Adaptor Board for information on the touchscreen controller and the CLCD displays.) • an optional RealView Logic Tile.
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Hardware Description See Color LCD Controller, CLCDC on page 4-47 and the ARM926EJ-S Development Chip Reference Manual for interface details. The ARM926EJ-S PXP Development Chip also contains a MOVE video encoding coprocessor and a MBX graphics accelerator, see the ARM MOVE Coprocessor Technical Reference Manual and ARM MBX HR-S Graphics Core Technical Reference Manual for details. Table 3-14 Display interface signals Signal Description CLD[23:0] LCD panel data.
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Hardware Description Table 3-14 Display interface signals (continued) Signal Description TSSCLK Clock to touchscreen controller. TSMOSI Data from touchscreen controller. TSMISO Data from touchscreen controller. TSnDAV Touchscreen controller data available signal. TSnPENIRQ Touchscreen controller pen down interrupt. TSnKPADIRQ Touchscreen controller key pressed interrupt. TSnSS Touchscreen controller chip select.
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Hardware Description 3.9 DMA On-chip peripherals in the ARM926EJ-S PXP Development Chip use DMA channels 6–15. DMA control signals for channels 0–5 are passed to the RealView Logic Tile connectors and signals for channels 0–2 are also passed to the DMA mapping multiplexors in the FPGA. Figure 3-27 on page 3-66 shows the DMA architecture. See also Direct Memory Access Controller and mapping registers on page 4-52. Caution The FPGA and RealView Logic Tile share the signals for channels 0 to 2.
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Hardware Description Figure 3-27 DMA channels The DMA control signals for external devices are listed in Table 3-15 on page 3-67. Note Some FPGA peripherals do not use all of the DMA control signals. The USB controller, for example, uses only the DMACSREQ and DMACCLR signals. 3-66 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description The names of DMA control signals change as they pass through the mapping logic in the FPGA. For the USB controller, DMACSREQ signals correspond to USBDREQ[1:0] and the DMACCLR signals correspond to USBDACK[1:0]. Table 3-15 DMA signals for external devices ARM DUI 0224I Signal Description DMACBREQ[5:0] Burst request inputs to DMAC for channels 5 to 0. DMACLBREQ[5:0] Last burst request inputs to DMAC for channels 5 to 0.
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Hardware Description 3.10 Ethernet interface The Ethernet interface is implemented with a SMC LAN91C111 10/100 Ethernet single-chip MAC and PHY. This is provided with a slave interface to the system bus by the FPGA. The internal registers of the LAN91C111 are memory-mapped onto the AHB M2 bus and occupy 16 word locations at 0x10010000. The isolating RJ45 connector incorporates two network status LEDs.
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Hardware Description Table 3-16 Ethernet signals (continued) 3.10.1 Signal Description TPI+, TPI- Signal from interface to controller. LEDA, LEDB Activity indicator LEDs. The function of the LEDs can be configured by writing to a LAN91C111 register. ETHRESET Reset signal to LAN91C111. ETHARDY Asynchronous ready signal. ETHSRDY Synchronous ready signal. ETHnRDYRTN Signals to the controller to complete synchronous read cycles. ETHnADS Latches address to controller.
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Hardware Description The controller uses a local VL-Bus host interface with a bridge to the AHB bus provided by the FPGA. The FPGA generates the appropriate access control signals for the host side of the Ethernet controller. The VL-Bus is a synchronous bus that supports 32-bit accesses. The LAN91C111 is a little-endian device. The default configuration for the system bus is also little-endian.
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Hardware Description 3.11 GPIO interface The GPIO signals GPx_[7:0] from the ARM926EJ-S PXP Development Chip are connected to the GPIO connectors and the RealView Logic Tile as shown in Figure 3-29. The GPIO signals are also connected to the expansion connector for the optional RealView Logic Tile. This enables you to use the GPIO signals with custom logic you implement in the tile.
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Hardware Description 3.12 Interrupts The ARM926EJ-S PXP Development Chip contains the primary interrupt controller and a secondary interrupt controller is in the FPGA, see Figure 3-30. Figure 3-30 External and internal interrupt sources 3-72 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description The primary interrupt controller manages interrupts from internal devices and provides 11 pins for use by the external secondary interrupt controller and multiplexor present in the FPGA. VICINTSOURCE31 is the output from the secondary controller. VICINTSOURCE[30:21] can be driven from individual interrupt signals from peripherals in the FPGA or on a RealView Logic Tile.
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Hardware Description 3.13 Keyboard/Mouse Interface, KMI The Keyboard and Mouse Interfaces (KMI) are implemented with two PrimeCells incorporated into the FPGA. This is shown in Figure 3-31. Figure 3-31 KMI block diagram See also Keyboard and Mouse Interface, KMI on page 4-67 and the ARM PrimeCell PS2 Keyboard Mouse Controller (PL050) Technical Reference Manual. 3-74 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description 3.14 Memory Card Interface, MCI Two ARM PL180 PrimeCell MCIs provide the interface to two multimedia (MMC) or Secure Digital (SD) cards. Each interface can be driven as either an MMC or SD interface. 3.14.1 MMC or SD operation The MMC socket provides nine pins that connect to the card when it is inserted into the socket. (The nine-way socket is compatible with SD cards. However MMC uses only seven of the nine pins.
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Hardware Description 3.14.2 Card insertion and removal Insert the card into the socket with the contacts face down for the connector on the top of the PB926EJ-S or face up for the bottom connector. Cards are normally labelled on the top surface and provide an arrow to indicate the correct way to insert them. Remove the card by gently pressing it into the socket. It springs back and can be removed. This ensures that the card detection switches within the socket operate correctly. 3.14.
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Hardware Description Table 3-18 MMC signals Signal Description MCIPWRx Enables supply voltage to card. MCIxCMD Command selection. CARDINx Card detect signal. Read the current state from SYS_MCI. MCIxDAT[3:0] Card data bus. WPROTx Write protection indication. Read the current state from SYS_MCI. MCICLKx Clock to card. See MMC and SD flash card interface on page A-8 for details of the MMC/SD card socket and pin numbering.
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Hardware Description 3.15 PCI interface The PCI subsystem enables you to use PCI expansion cards with the PB926EJ-S and the PCI enclosure. PCI bridges pass valid accesses between the PB926EJ-S and the PCI bus. The slave bridge connected to the AHB M2 bus recognizes addresses 0x41000000 to 0x6FFFFFFF as being intended for a target within the PCI address space of the memory map, and passes accesses within this region to the PCI bus.
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Hardware Description 3.16 Serial bus interface The FPGA implements a serial bus interface that is used to identify the memory expansion modules and read and set the time-of-year clock. Each device on the serial bus has its own slave address. The unique address for each slave on the serial bus is shown in Table 3-19.
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Hardware Description 3.17 Smart Card interface, SCI The ARM926EJ-S PXP Development Chip contains a PrimeCell Smart Card Interface (SCI). A second SCI is implemented in the FPGA. There are two sets of Smart Card connectors on the board, J25/J48 and J26/J49. Only one header is fitted for each channel. The connector numbers refer to different size connectors that can be can be fitted. (J25 and J26 are large connectors. J48 and J49 are small connectors.
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Hardware Description Figure 3-35 SCI block diagram You can set the Smart Card interface voltage to operate at 5V, 3.3V or 1.8V by setting jumpers on J27 (for SCI0) and J50 (for SCI1). • Connect pins AB for 3.3V operation • Connect pins CB for 5V operation • omit the link for 1.8V operation. 3-82 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description The default setting is linking pins AB. Both 3.3V and 5V cards will function with this setting. Note The Smart Card VCC is switched on and off by the SCIVCCENx signal from the PrimeCell. See also Smart Card Interface, SCI on page 4-88 and the SCI PrimeCell PL131 Technical Reference Manual. Table 3-21 Smart Card interface signals ARM DUI 0224I Signal Description SCICLKINx PrimeCell SCI clock input. nSCICLKENx Tristate output buffer control for clock (active LOW).
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Hardware Description 3.18 Synchronous Serial Port, SSP 3V3 TSMISO TSMOSI TSSCLK LCDDATnCOM TSnKPADIRQ TSnPENIRQ TSnDAV TSnSS CLCD expansion FPGA AHB M2 SSPRXD SSPCLKIN SSPFSSIN SSPnCS Buffers ARM926EJ-S Dev. Chip PL022 SSPC PrimeCell SSPCLKOUT SSPFSSOUT SSPTXD nSSPCTLOE nSSPOE J29, SSP expansion SSPCLKOUT SSPFSSOUT SSPTXD nSSPCTLOE nSSPOE SSPRXD SSPCLKIN SSPFSSIN nDRVINEN1 Logic Tile The ARM926EJ-S PXP Development Chip contains a PrimeCell SSP controller.
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Hardware Description Table 3-22 SSP signal descriptions Name Description SSPnCS Chip select to external device connected to SSP controller. SSPFSSOUT PrimeCell SSP frame or slave select output (master). SSPCLKOUT PrimeCell SSP clock output (master). SSPRXD PrimeCell SSP receive data input. SSPTXD PrimeCell SSP transmit data output. nSSPCTLOE Output enable signal (active LOW) for the SSPCLKOUT output from the PrimeCell SSP.
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Hardware Description Note Although it is possible to connect both the CLCD adaptor board and an off board SSP device at the same time, care must be taken to ensure the correct SSP interface protocol is used when communicating with each device. The interface can be shared because the data from the touch screen controller data (TSMISO) is buffered with an open drain driver into SSPRXD. • Synthesized SSP peripherals in a RealView Logic Tile FPGA. See Appendix F RealView Logic Tile.
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Hardware Description 3.19 User switches and LEDs The FPGA provides a switch and LED register that enables you to read the general-purpose pushbutton switch and the user switches (S6) and light the user LEDs (located next to switch S6). See Figure 1-1 on page 1-3 for the location of the switches and LEDs. Figure 3-37 shows the interface. Note Switch S6-1 and S6-2 are used to control the Boot Monitor. See Boot Monitor configuration on page 2-7.
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Hardware Description 3.20 UART interface Three UARTs (SER0, SER1, and SER2) are provided by the ARM926EJ-S PXP Development Chip. A fourth serial interface, SER3, is implemented with a PrimeCell UART incorporated into the system controller FPGA.
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RS232 UART1x output signals UART1x input signals UART2x output signals UART2x input signals SER1x SER1x SER2x SER2x Versatile Logic Tile J10A SER0x SER0x J10B RS232 UART0 IrDA signals UART0x output signals UART0x input signals J11A nDRVINEN1 nDRVINEN0 RS232 PL011 PL011 PL011 PrimeCell PrimeCell PrimeCell ARM926EJ-S Dev.
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Hardware Description Figure 3-40 Simplified interface for UART[3:1] See also UART on page 4-97 and the ARM PrimeCell UART (PL011) Technical Reference Manual. The signals associated with the UART interface are shown in Table 3-23. Table 3-23 Serial interface signal assignment 3-90 Signal Description nDRVINEN0 This signal can be driven HIGH by an attached logic tile.
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Hardware Description Table 3-23 Serial interface signal assignment (continued) Signal Description SERx_DCDb Data carrier detect SERx_RXD Receive data SERx_RIb Ring indicator a. For UART1, UART2, and UART3, the DTR and DSR signals are connected together and are not input to the ARM926EJ-S Dev. Chip or FPGA. b. For UART1, UART2, and UART3, the DCD and RI signals are not connected to the ARM926EJ-S Dev. Chip or FPGA. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description 3.21 USB interface The FPGA provides the bus interface to an external OTG243 USB controller. Three USB interfaces are provided on the PB926EJ-S, see Figure 3-41. The internal registers of the controller are memory-mapped onto the AHB M2 bus at 0x10020000. Figure 3-41 OTG243 block diagram OTG243 USB port 1 provides an OTG device interface and connects to J6.
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Hardware Description The signals associated with the USB interfaces are shown in Table 3-24.
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Hardware Description 3.
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Hardware Description JTAG connector FPGA debug CFGEN LED Trace Port Adapter connector J32 CONFIG LINK USB debug BUSY LED AHB monitor ChipScope USB debug ON LED USB debug connector Figure 3-42 Test and debug connectors, links, and LEDs Note The CONFIG link is a switch on some board versions. If so, placing the switch in the OFF position is the same as no link fitted. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Hardware Description 3.22.1 JTAG and USB debug port support The PB926EJ-S supports debugging using embedded or external hardware. The debugging interface can be controlled by: JTAG hardware The RealView Debugger and the AXD debugger, for example, use an external interface box, such as RealView ICE or Multi-ICE, to connect to the JTAG connector. If you are using an external JTAG debug tool, the embedded debug hardware is disabled. USB debug port The USB debug port is embedded on the PB926EJ-S.
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Hardware Description • the JTAG signals are routed through the ARM926EJ-S PXP Development Chip • a debugger, RealView Debugger for example, controls the scan chain • The PLDs and FPGAs are not visible on the scan chain unless they contain debuggable devices • If RealView Logic Tiles are present and have debuggable devices, the D_x signals are part of their JTAG scan chain • the FPGAs in the system load their images from configuration flash.
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Hardware Description The FPGAs are volatile. In normal mode, they load their configuration from nonvolatile flash memory. In configuration mode, they can be loaded from either JTAG or the configuration flash memory. Note The configuration flash memory does not have a JTAG port, but it can be programmed using JTAG by loading a flash-loader design into the FPGAs and PLDs. The flash-loader can then transfer data from the JTAG programming utility to the configuration flash. After configuration you must: 1.
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Hardware Description Table 3-25 JTAG related signals (continued) Name Description Function RTCK Return TCK (to JTAG equipment) Some devices sample TCK and delay the time at which a component actually captures data. Using a mechanism called adaptive clocking, the RTCK signal is returned by the core to the JTAG equipment, and the TCK is not advanced until the core has captured the data. In adaptive clocking mode, RealView ICE or Multi-ICE waits for an edge on RTCK before changing TCK.
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Hardware Description Table 3-25 JTAG related signals (continued) Name Description Function DBGACK Debug acknowledge (to JTAG equipment) DBGACK indicates to the debugger that the processor core has entered debug mode. It is provided for compatibility with third-party JTAG equipment. GLOBAL_DONE FPGA configured GLOBAL_DONE is an open-collector signal that indicates when FPGA configuration is complete. Although this signal is not a JTAG signal, it does affect nSRST.
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Hardware Description 3.22.2 ChipScope integrated logic analyzer The ChipScope connector (J33) enables you to connect a ChipScope compatible analyzer to the configuraion scan chain while a JTAG debugger is connected to the debug scan chain. This enables you to debug the FPGAs on stacked tiles while examining code on the CPU. Note In debug mode: • the ChipScope connector is enabled • the FPGA on the baseboard is excluded from the configuration scan chain.
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Chapter 4 Programmer’s Reference This chapter describes the memory map and the configuration registers for the peripherals in the ARM926EJ-S PXP Development Chip.
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Programmer’s Reference • • • • • • • • • • • • • MultiPort Memory Controller, MPMC on page 4-71 PCI controller on page 4-74 Real Time Clock, RTC on page 4-85 Serial bus interface on page 4-86 Smart Card Interface, SCI on page 4-88 Synchronous Serial Port, SSP on page 4-89 Synchronous Static Memory Controller, SSMC on page 4-91 System Controller on page 4-95 Timers on page 4-96 USB interface on page 4-99 UART on page 4-97 Vector Floating Point, VFP9 on page 4-100 Watchdog on page 4-101.
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Programmer’s Reference 4.1 Memory map The locations for memory, peripherals, and controllers are listed in Table 4-1 and ARM Data bus memory map on page 4-8. There are multiple buses in the ARM926EJ-S PXP Development Chip. Not all of the buses can access all of the memory regions. See AHB bridges and the bus matrix on page 3-10 and the ARM926EJ-S Reference Manual for details on the bus matrix and bus accesses.
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Programmer’s Reference Table 4-1 Memory map (continued) Interrupta PIC and SIC Region size Peripheral Location Multimedia Card Interface 0 (MMCI0) FPGA MCI0A: PIC 22, SIC 22 MCI0B: SIC 1 0x10005000– 0x10005FFF 4KB Keyboard/Mouse Interface 0 FPGA SIC 3 0x10006000– 0x10006FFF 4KB Keyboard/Mouse Interface 1 FPGA SIC 4 0x10007000– 0x10007FFF 4KB Character LCD Interface FPGA SIC 7 0x10008000– 0x10008FFF 4KB UART 3 FPGA SIC 6 0x10009000– 0x10009FFF 4KB Smart Card1 Interface FPGA SI
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Programmer’s Reference Table 4-1 Memory map (continued) Peripheral Location Interrupta PIC and SIC DMA Controller Dev. chip PIC 17 0x10130000– 0x1013FFFF 64KB Vectored Interrupt Controller (PIC) Dev. chip - 0x10140000– 0x1014FFFF 64KB Reserved FPGA - 0x10150000– 0x101CFFFF 64KB AHB Monitor Interface Dev. chip - 0x101D0000– 0x101DFFFF 64KB System Controller Dev. chip - 0x101E0000– 0x101E0FFF 4KB Watchdog Interface Dev.
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Programmer’s Reference Table 4-1 Memory map (continued) Peripheral Location Interrupta PIC and SIC UART 0 Interface Dev. chip PIC 12 0x101F1000– 0x101F1FFF 4KB UART 1 Interface Dev. chip PIC 13 0x101F2000– 0x101F2FFF 4KB UART 2 Interface Dev. chip PIC 14 0x101F3000– 0x101F3FFF 4KB Synchronous Serial Port Interface Dev. chip PIC 11 0x101F4000– 0x101F4FFF 4KB Reserved - - 0x101F5000– 0x13FFFFFF 94MB Reserved for use by RealView Logic Tile bus AHB M2.
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Programmer’s Reference Table 4-1 Memory map (continued) Peripheral Location PCI interface bus windows Interrupta PIC and SIC Address Region size PCI PCI3: PIC 30, SIC 30 PCI2: PIC 29, SIC 29 PCI1: PIC 28, SIC 28 PCI0: PIC 27, SIC 27 0x41000000– 0x6FFFFFFF 752MB MPMC Chip Selects 2–3, expansion dynamic memory Expansion memory - 0x70000000– 0x7FFFFFFF 256MB RealView Logic Tile expansion ( AHB M1 bus). (If a RealView Logic Tile is installed, accesses in this range must be decoded by the tile.
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Programmer’s Reference 4.2 Configuration and initialization This section describes how the ARM926EJ-S PXP Development Chip and external memory and peripherals are configured and initialized at power on. See Status and system control registers on page 4-17 and Boot Select Register, SYS_BOOTCS on page 4-34 for details on configuration operations that can be performed after the system has started. See also Configuration control on page 3-7 and Configuration registers SYS_CFGDATAx on page 4-25. 4.2.
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Programmer’s Reference Configuration switch S1 modifies the memory map of static memory at reset as listed in Table 4-2. S1-1 controls BOOTCSSEL0 and S1-2 controls BOOTCSSEL1. If a switch is ON, the corresponding BOOTCSSEL signal is HIGH. Table 4-2 Selecting the boot device S1-2 S1-1 Device OFF OFF Reserved.
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Programmer’s Reference 3. Clear the DEVCHIP REMAP bit by writing a 1 to bit 8 of the System Controller register at 0x101E0000. This removes the remapping of boot memory to 0x0. 4. Initialize the MPMC controller with the appropriate values for the type of dynamic RAM used. 5. Use the SDRAM at location 0x0 to hold additional initialization code and the stack for the application. 6. Jump to the initialization code in SDRAM. 7. Set up all static chip select control registers.
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Programmer’s Reference Booting from NOR flash 1 The memory maps for S1-2 OFF (BOOTSEL1 LOW) and S1-1 ON (BOOTSEL0 HIGH) are shown in Figure 4-2.
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Programmer’s Reference Booting from static expansion memory The memory maps for S1-2 ON (BOOTSEL1 HIGH) and S1-1 OFF (BOOTSEL0 LOW) are shown in Figure 4-3.
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Programmer’s Reference Booting from AHB expansion memory The memory maps for S1-2 ON (BOOTSEL1 HIGH) and S1-1 ON (BOOTSEL0 HIGH) are shown in Figure 4-4. The AHB expansion memory on the RealView Logic Tile is on the AHB M2 bus. Note If you are booting from static memory on a RealView Logic Tile, jump to the natural address of your expansion memory before disabling DEVCHIP REMAP.
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Programmer’s Reference 4.2.2 Memory characteristics Some memory access characteristics, for example chip select polarity and memory width, are set by the CONFIGDATA signals. Changing these values might be required, for example, if you are booting from expansion memory. The signal states are determined by the SYS_CFGDATAx registers.
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Programmer’s Reference Memory banks Table 4-3 lists the controller memory banks, chip selects, and memory range.
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Programmer’s Reference 4.3 Status and system control registers The PB926EJ-S status and system control registers enable the processor to determine its environment and to control some on-board operations. The registers, listed in Table 4-4 on page 4-18, are located from 0x10000000. See also the ARM PrimeCell System Controller (SP810) Technical Reference Manual for details of control registers in the SP810 System Controller that is in the ARM926EJ-S PXP Development Chip.
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Programmer’s Reference Table 4-4 Register map for system control registers Name Address Accessa Reset level SYS_ID 0x10000000 Read only - System Identity. See ID Register, SYS_ID on page 4-21. SYS_SW 0x10000004 Read only - Bits [7:0] map to S6 (user switches) SYS_LED 0x10000008 Read/Write 6 Bits [7:0] map to user LEDs (located next to S6) SYS_OSC0 0x1000000C Read/Write Lockable 2 Settings for the ICS307 programmable oscillator chip OSC0.
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Programmer’s Reference Table 4-4 Register map for system control registers (continued) Name Address Accessa Reset level SYS_FLAGS 0x10000030 Read only 6 General-purpose flags (reset by any reset). See Flag registers, SYS_FLAGx and SYS_NVFLAGx on page 4-30. SYS_FLAGSSET 0x10000030 Write 6 Set bits in general-purpose flags. SYS_FLAGSCLR 0x10000034 Write 6 Clear bits in general-purpose flags. SYS_NVFLAGS 0x10000038 Read only 0 General-purpose nonvolatile flags (reset only on power up).
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Programmer’s Reference Table 4-4 Register map for system control registers (continued) Reset level Name Address Accessa SYS_OSCRESET0 0x1000008C Read/Write Lockable 0 Value to load into the SYS_OSC0 register if the DEV CHIP RECONFIGURE pushbutton is pressed (APPLYCFGWORD active). At power-on reset, the SYS_OSCRESET0 is loaded with the same default value as used for SYS_OSC0.
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Programmer’s Reference 4.3.1 ID Register, SYS_ID The SYS_ID register at 0x10000000 is a read-only register that identifies the board manufacturer, board type, and revision. Figure 4-5 shows the bit assignment of the register. Figure 4-5 ID Register, SYS_ID Table 4-5 describes the PB926EJ-S ID Register assignment. Table 4-5 ID Register, SYS_ID bit assignment 4.3.
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Programmer’s Reference 4.3.3 LED Register, SYS_LED Use the SYS_LED register at 0x10000008 to set the user LEDs. (The LEDs are located next to user switch S6.) Set the corresponding bit to 1 to illuminate the LED. Figure 4-7 SYS_LED 4-22 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Programmer’s Reference 4.3.4 Oscillator registers, SYS_OSCx The oscillator registers, SYS_OSC0 to SYS_OSC4, at 0x1000000C–0x1000001C are read/write registers that control the frequency of the clocks generated by the ICS307 programmable oscillators. A serial interface transfers the values in the registers to the programmable oscillators when a reset occurs.
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Programmer’s Reference 4.3.5 Lock Register, SYS_LOCK The SYS_LOCK register at 0x10000020 locks or unlocks access to the following registers: • Oscillator registers, SYS_OSCx • Reset values for oscillators, SYS_OSCRESETx • Configuration registers, SYS_CFGDATAx • Reset control register, SYS_RESETCTL The control registers cannot be modified while they are locked. This mechanism prevents the registers from being overwritten accidently. The registers are locked by default after a reset.
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Programmer’s Reference 4.3.6 100Hz Counter, SYS_100HZ The SYS_100HZ register at 0x10000024 is a 32-bit counter incremented at 100Hz. The 100Hz reference is derived from the 32KHz crystal oscillator. The register is set to zero by a reset. 4.3.7 Configuration registers SYS_CFGDATAx The read/write registers SYS_CFGDATA1 and SYS_CFGDATA2 contain configuration data that is applied to the ARM926EJ-S PXP Development Chip HDATAM1 and HDATAM2 pins when the DEV CHIP RECONFIG pushbutton is pressed.
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Programmer’s Reference Table 4-8 Configuration register 1 Bits Power-on reset state Description [31:24] - Reserved for future use. [23:16] b11110000 HCLKCTRL[7:0], clock selection multiplexors control. The value of b1111000 selects GLOBALCLK as source for the external clocking of the AHB M1, M2, and S bridges when they are operating in asynchronous mode.
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Programmer’s Reference Table 4-9 Configuration register 2 Bits Power-on reset state Description [31:29] - Reserved for future use. [28] b0 CFGINCROVERRIDES, AMBA on-chip AHB slave bridge. Override burst transfer with INCR mode (active HIGH). [27] b0 CFGINCROVERRIDEM2, AMBA off-chip AHB bridge 2. Override burst transfer with INCR mode (active HIGH). [26] b0 CFGINCROVERRIDEM1, AMBA off-chip AHB bridge 1. Override burst transfer with INCR mode (active HIGH). [25] b0 CFGAHBPASST, AMBA bridges.
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Programmer’s Reference Table 4-9 Configuration register 2 (continued) Bits Power-on reset state [17:15] b001 Description CFGHCLKEXTDIVSEL[2:0], clock control. Sets the HCLK to HCLKEXT divide ratio. The divide value is set as follows: b000 = 1 b001 = 2 b010 = 3 b011 = 4 b100 = 5 b101 = 6 b110 = 7 b111 = 8 Note The default SYS_OSC0 setting gives an OSC0 clock of 35MHz.
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Programmer’s Reference Table 4-9 Configuration register 2 (continued) Bits Power-on reset state Description [6] b1 CFGBRIDGEMEMMAP, AMBA bridge mapping. Reserved. Must be set to 1. [5] b0 CFGREMAPDYEXEN, dynamic memory and expansion memory alias enable (see Remapping of boot memory on page 4-9). When HIGH and CFGREMAPSTEXEN is LOW, then dynamic memory is aliased to 0x00000000. When HIGH and CFGREMAPSTEXEN is HIGH, then expansion memory is aliased to 0x00000000. Note This bit is read-only.
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Programmer’s Reference 4.3.8 Flag registers, SYS_FLAGx and SYS_NVFLAGx The registers shown in Table 4-10 provide two 32-bit register locations containing general-purpose flags. You can assign any meaning to the flags.
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Programmer’s Reference 4.3.9 Reset Control Register, SYS_RESETCTL The SYS_RESETCTL register at 0x10000040 sets reset depth and programmable soft reset, see Reset controller on page 3-22 and Reset level on page 3-24. The function of the register bits are shown in Table 4-11. You must unlock the register (see Lock Register, SYS_LOCK on page 4-24) before the register contents can be modified. Figure 4-12 SYS_RESETCTL Table 4-11 Reset level control Bits Access Description [31:9] Read write Reserved.
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Programmer’s Reference Figure 4-13 SYS_MCI Table 4-12 MCI control 4.3.12 Bits Access Description [31:5] - Reserved. Use read-modify-write to preserve value. [4] - Reserved (data multiplex) [3] Read Write protect 1 [2] Read Write protect 0 [1] Read Card detect 1 [0] Read Card detect 0 Flash Control Register, SYS_FLASH Bit 0 of the SYS_FLASH register at 0x1000004C controls write protection of NOR flash devices. The function of the register bits are shown in Table 4-13.
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Programmer’s Reference Figure 4-14 SYS_CLCD Table 4-14 SYS_CLCD register Bits Access Description [31:14] - Reserved. Use read-modify-write to preserve value. [13] Read TSnDAV status, LOW indicates that data is available for reading from the touchscreen. [12:8] Read CLCDID[4:0], returns the setting of the ID links on the CLCD adaptor board Value 0 1 2 3-31 Display 320x240 QVGA 640x480 VGA 220x176 QCIF Reserved [7] Read/write SSP expansion chip select.
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Programmer’s Reference 4.3.14 2.2 inch LCD Control Register SYS_CLCDSER The SYS_CLCDSER register at 0x10000054 controls the interface to the serial power-on logic in the 2.2inch display on the LCD adaptor board. See Table 4-15 and LCD power control on page C-7. Use this register to configure the 2.2inch display at power-on. Figure 4-15 SYS_CLCDSER Table 4-15 SYS_CLCDSER register 4.3.15 Bits Access Description [31:7] - Reserved. Use read-modify-write to preserve value.
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Programmer’s Reference Figure 4-16 SYS_BOOTCS Table 4-16 BOOT configuration switches Bits Access Description [31:8] - Reserved. Use read-modify-write to preserve value. [7] Read Stack image (RealView Logic Tile image 0 or 1). The default is tile image 0 (S1-8 OFF). [6:5] Read FPGA image to load on power on. b00 b01 b10 b11 Image Image Image Image 0 (default, S1-7 and S1-6 OFF) 1 2 3 [4] Read Low-frequency startup mode.
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Programmer’s Reference 4.3.16 24MHz Counter, SYS_24MHZ The SYS_24MHZ register at 0x1000005C provides a 32-bit count value. The count increments at 24MHz frequency from the 24MHz crystal reference output REFCLK24MHZ from OSC0. The register is set to zero by a reset. 4.3.17 Miscellaneous System Control Register, SYS_MISC The SYS_MISC register at 0x10000060 provides miscellaneous status and control signals as shown in Table 4-17.
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Programmer’s Reference Table 4-17 SYS_MISC (continued) 4.3.18 Bits Access Description [2] Read/write FPGA remap control (FPGA_REMAP) [1] Read RTCOUT signal from the external DS1338 real-time clock. This 32kHz signal can be used as a timer. [0] Read nTILEDET signal. Pulled LOW if a RealView Logic Tile is connected to the expansion headers.
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Programmer’s Reference Table 4-19 SYS_DMAPSRx, DMA mapping register format Bit Access Description [31:8] - Reserved. Use read-modify-write to preserve value. [7] Read/write Set to 1 to enable mapping of external peripheral DMA signals to the DMA controller channel [6:5] - Reserved. Use read-modify-write to preserve value.
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Programmer’s Reference 4.3.19 Oscillator reset registers, SYS_OSCRESETx The oscillator reset registers, SYS_OSCRESET0 to SYS_OSCRESET4, at 0x1000008C–0x1000009C are read/write registers that control the frequency of the clocks generated by clock generators OSC0, OSC1, OSC2, OSC3, and OSC4 if the DEV CHIP RECONFIG pushbutton is pressed. Figure 4-19 shows the bit assignment of the registers.
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Programmer’s Reference 4.3.20 Oscillator test registers, SYS_TEST_OSCx The oscillator test registers, SYS_TEST_OSC0 to SYS_TEST_OSC4, provide 32-bit count values. The count increments at frequency of the corresponding ICS307 programmable oscillator. The registers are set to zero by a reset.
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Programmer’s Reference 4.4 AHB monitor The AHB monitor observes the activity on the AHB bus signals in the bus matrix and produces real-time information that is exported off-chip. It also records statistical information into counter registers that are accessible through the AHB interface.
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Programmer’s Reference 4.5 Advanced Audio CODEC Interface, AACI The PrimeCell Advanced Audio CODEC Interface (AACI) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. Table 4-22 AACI implementation 4.5.1 Property Value Location FPGA (the CODEC is an external LM4549). Memory base address 0x10004000 Interrupt 24 on secondary controller. DMA Selectable as channel 0,1, or 2. See DMA peripheral map registers, SYS_DMAPSRx on page 4-37.
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Programmer’s Reference Table 4-23 Modified AACI PeriphID3 register Bit Access Description [31:8] - Not used. [7:6] - Reserved. Use read-modify-write to preserve value. [5:3] Read FIFO depth in compact mode: b000 b001 b010 b011 b100 b101 b110 b111 [2:0] Read Number of channels: b000 b001 b010 b011 b100 b101 b110 b111 ARM DUI 0224I 8 16 32 64 128 256 (default) 512 1024 4 1 (default) 2 3 4 5 6 7 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Programmer’s Reference 4.6 Character LCD display This is a custom peripheral that provides an interface to a standard HD44780 16 x 2 character LCD module. Table 4-24 Character LCD display implementation Property Value Location FPGA Memory base address 0x10008000 Interrupt NA DMA NA Release version custom logic Reference documentation datasheet for the Hitachi HD44780 display (see also Character LCD controller on page 3-59) Note The HD44780 display interface is very slow.
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Programmer’s Reference The control and data registers for the character LCD interface are listed in Table 4-25. Table 4-25 Character LCD control and data registers Address Name Type Description 0x10008000 CHAR_COM Write command, read busy status A write to this address will cause a write to the HD44780 command register some cycles later.A read from this address will cause a read from the HD44780 busy register some cycles later. Note The data read from this address is not valid LCD register data.
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Programmer’s Reference An overview of the commands available is listed in Table 4-26. Table 4-26 Character LCD display commands Command Bit pattern Clear display b00000001 Clears entire display and sets display RAM address counter to zero. Return home b0000001x Sets display RAM address counter to zero and returns the cursor to the first character position. Display RAM contents are not erased. Entry mode set b000001DS Sets cursor move direction to increment (D HIGH) or decrement (D LOW).
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Programmer’s Reference 4.7 Color LCD Controller, CLCDC The PrimeCell Color LCD Controller (CLCDC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. Table 4-27 CLCDC implementation Property Value Location ARM926EJ-S PXP Development Chip Memory base address 0x10120000 Note There are also LCD power control registers at 0x10000050 and 0x10000054. See CLCD Control Register, SYS_CLCD on page 4-32 and 2.2 inch LCD Control Register SYS_CLCDSER on page 4-34.
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Programmer’s Reference 4.7.1 PrimeCell Modifications The register map for the variant of the PL110 used in the ARM926EJ-S PXP Development Chip is not the same as that listed for the standard PL110. The differences are listed in Table 4-28. Table 4-28 PrimeCell CLCDC register differences Address (Dev. Chip) Reset value (Dev.
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Programmer’s Reference Table 4-29 Values for different display resolutions (continued) Display resolution CLCDCLK frequency and SYS_OSCCLK4 register value CLCD_TIM0 register at 0x10120000 CLCD_TIM1 register 0x10120004 CLCD_TIM2 register at 0x10120008 SVGA (800x600) on SVGA 36MHz, 0x2CAC 0x1313A4C4 0x0505F657 0x071F1800 Epson 2.2in panel QCIF (176x220) 10MHz, 0x2C2A 0x00000128 0x000000DB 0x04AF1800 Sanyo 3.
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Programmer’s Reference Table 4-30 Assignment of display memory to R[7:0], G[7:0], and B[7:0] (continued) 4-50 Memory bit 8/8/8 1/5/5/5 5/6/5 red (lsb) 5/6/5 blue (lsb) 23 B7 (msb) pixel1 G3 pixel1 G2 pixel1 G2 22 B6 pixel1 G2 pixel1 G1 pixel1 G1 21 B5 pixel1 G1 (lsb) pixel1 G0 (lsb) pixel1 G0 (lsb) 20 B4 pixel1 R5 (msb) pixel1 R5 (msb) pixel1 B5 (msb) 19 B3 pixel1 R4 pixel1 R4 pixel1 B4 18 B2 pixel1 R3 pixel1 R3 pixel1 B3 17 B1 pixel1 R2 pixel1 R2 pixel1 B2 16 B0
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Programmer’s Reference Table 4-31 PL110 hardware playback mode Dev.
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Programmer’s Reference 4.8 Direct Memory Access Controller and mapping registers The PrimeCell Direct Memory Access Controller (DMAC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. The DMAC is located in the ARM926EJ-S PXP Development Chip and three DMA mapping registers are located in the FPGA.
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Programmer’s Reference Table 4-33 shows the DMA channel allocation.
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Programmer’s Reference Figure 4-21 SYS_DMAP0-2 mapping register format Table 4-34 DMA mapping register format Bit Access Description [31:8] - Reserved [7] Read/write Set to 1 to enable mapping [6:5] - Reserved [4:0] Read/write FPGA peripheral mapped to this channel b00000 = AACI Tx b00001 = AACI Rx b00010 = USB Aa b00011 = USB B b00100 = MCI 0 b00101 = MCI 1 b00110 = UART3 Tx b00111 = UART3 Rx b01000 = SCI0 int A b01001 = SCI0 int B b01010–b11111 Reserved a.
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Programmer’s Reference 4.9 Ethernet The Ethernet interface is implemented in an external SMC LAN91C111 10/100 Ethernet single-chip MAC and PHY. The internal registers of the LAN91C111 are memory-mapped onto the AHB M2 bus and occupy 16 word locations at 0x10010000. Table 4-35 Ethernet implementation Property Value Location Board (LAN91C111 chip) Memory base address 0x10010000 Interrupt 25 on both the primary and secondary controllers DMA None, use memory to memory DMA to access the buffer memory.
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Programmer’s Reference 4.10 General Purpose Input/Output, GPIO The PrimeCell General Purpose Input/Output (GPIO) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.
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Programmer’s Reference 4.11 Interrupt controllers The PrimeCell Vectored Interrupt Controller (VIC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. The ARM926EJ-S has two interrupt signals: • FIQ for fast, low latency interrupt handling • IRQ for more general interrupts. The VIC in the ARM926EJ-S PXP Development Chip accepts interrupts from peripherals located on the RealView Logic Tiles or in the FPGA and generates the FIQ and IRQ signals.
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Programmer’s Reference Table 4-38 SIC implementation (continued) 4.11.1 Property Value DMA NA Release version custom logic Reference documentation Secondary interrupt controller on page 4-61 and Interrupts on page 3-72) Primary interrupt controller The primary interrupt control registers are listed in Table 4-39. For more detail on the primary interrupt controller, see the ARMPL190 VIC Technical Reference Manual.
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Programmer’s Reference Table 4-39 Primary interrupt controller registers (continued) Address Name Access Description 0x10140300– 0x10140310 PICITCR, PICITIP1, PICITIP2, PICITOP1, PICITOP2, Read/write Test control registers 0x10140FE0– 0x10140FEC PICPeriphID0– PICPeriphID3 Read Peripheral identification registers 0x10140FF0– 0x10140FFC PICPCellID0– PICPCellID3 Read PrimeCell identification registers The bit assignments for the primary interrupt controller are shown in Figure 4-22 and Table 4
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Programmer’s Reference Table 4-40 Interrupt signals to primary interrupt controller (continued) 4-60 Bit Interrupt sourcea Description [26] VICINTSOURCE26 External interrupt signal from RealView Logic Tile or USB interrupt signal [25] VICINTSOURCE25 External interrupt signal from RealView Logic Tile or ETHERNET interrupt signal [24] VICINTSOURCE24 External interrupt signal from RealView Logic Tile or AACI interrupt signal [23] VICINTSOURCE23 External interrupt signal from RealView Logic Til
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Programmer’s Reference Table 4-40 Interrupt signals to primary interrupt controller (continued) Bit Interrupt sourcea Description [4] Timer 0 or 1 Timers on development chip [3] Comms TX Debug communications transmit interrupt. This interrupt indicates that the communications channel is available for the processor to pass messages to the debugger. [2] Comms RX Debug communications receive interrupt. This interrupt indicates to the processor that messages are available for the processor to read.
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Programmer’s Reference Table 4-41 Secondary interrupt controller registers (continued) Address Name Access Description 0x10003020 SIC_PICENABLE Read Read status of pass-through mask (allows interrupt to pass directly to the primary interrupt controller) 0x10003020 SIC_PICENSET Write Set bits HIGH to set the corresponding interrupt pass-through mask bits 0x10003024 SIC_PICENCLR Write Set bits HIGH to clear the corresponding interrupt pass-through mask bits The bit assignments for the seconda
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Programmer’s Reference Table 4-42 Interrupt signals to secondary interrupt controller (continued) 4.11.
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Programmer’s Reference Note Although the primary interrupt controller is a vectored interrupt controller (VIC), the examples in this section do not used vectored addresses. To determine an interrupt source, read the STATUS registers in the PIC and SIC to determine the interrupt controller that generated the interrupt. The sequence to determine and clear an interrupt is: 1. Determine the interrupt source by reading PIC_IRQStatus and SIC_STATUS.
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Programmer’s Reference // ... *SCI0_IMSC *PIC_IntEnable |= SCI0_CARDOUTIM; = PIC_SCI0; // Enable SCI0 card out interrupt // Enable the PIC SCI0 interrupt Example 4-2 shows how to detect the SCI1 card out interrupt signal from the secondary interrupt controller. Example 4-2 Pseudo code for SIC SCI1 card out interrupt If PIC_IRQStatus flags set, If PIC_SRC31 set, ...SIC interrupt handler If SIC_SCI1 set, ...SCI1 interrupt handler If SCI1_MIS,SCI1_CARDOUTIM flag set, ...
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Programmer’s Reference // . . . *SCI1_IMSC *SIC_ENSET *PIC_IntEnable 4-66 |= SCI1_CARDOUTIM; = SIC_SCI1; = PIC_SRC31; // Enable SCI1 card out interrupt // Enable the SIC SCI1 interrupt // Enable the PIC SIC interrupt Copyright © 2003-2010 ARM Limited. All rights reserved.
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Programmer’s Reference 4.12 Keyboard and Mouse Interface, KMI The ARM PrimeCell PS2 Keyboard/Mouse Interface (KMI) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. Two KMIs are present on the PB926EJ-S: KMI0 is used for keyboard input and KMI1 is used for mouse input.
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Programmer’s Reference 4.13 MBX The MBX Graphics Accelerator is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.
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Programmer’s Reference 4.14 MOVE video coprocessor The MOVE coprocessor is a video encoding acceleration coprocessor designed to accelerate motion-estimation algorithms within block-based video encoding schemes such as MPEG4 and H.263. Details of the MOVE coprocessor function are only available to licensees. Contact ARM for information on licensing. The release version of the MOVE accelerator is MOVE r3p0-00bet0 ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Programmer’s Reference 4.15 MultiMedia Card Interfaces, MCIx The PrimeCell Multimedia Card Interface (MCI) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. Table 4-45 MCI implementation 4-70 Property Value Location ARM926EJ-S PXP Development Chip MCI 0FPGA MCI 1. Memory base address 0x10005000 for MCI 0 0x1000B000 for MCI 1.
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Programmer’s Reference 4.16 MultiPort Memory Controller, MPMC The Multiport Memory Controller (MPMC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. Table 4-46 MPMC implementation Property Value Location ARM926EJ-S PXP Development Chip. Memory base address 0x10110000 Interrupt NA. DMA The MPMC does not use interrupts or DMA. DMA transfers, however, can be set up to access memory controlled by the MPMC. Release version ARM MPMC GX175 r0p0-00alp2.
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Programmer’s Reference Table 4-47 SDRAM register values 4-72 Address offset Register name Value Description +0x000 MPMCControl 0x1 Enabled +0x008 MPMCConfig 0x0 Little Endian +0x020 MPMCDynamicControl 0x3 MPMCCLKOUT runs continuously, CKE high +0x024 MPMCDynamicRefresh 0x22 544 cycles of HCLK between refreshes +0x028 MPMCDynamicReadConfig 0x111 command delayed strategy, using MPMCCLKDELAY, data capture on positive HCLK edge +0x030 MPMCDynamictRP 0x2 42.
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Programmer’s Reference Table 4-47 SDRAM register values (continued) ARM DUI 0224I Address offset Register name Value Description +0x144 MPMCDynamicRasCas2 0x202 CAS latency =2, RAS latency =2 +0x160 MPMCDynamicConfig3 0x5880 SDRAM32M16BRCX32 +0x164 MPMCDynamicRasCas3 0x202 CAS latency =2, RAS latency =2 +0x400 MPMCAHBControl0 0x0 - +0x408 MPMCAHBTimeOut0 0x2 Timeout value Copyright © 2003-2010 ARM Limited. All rights reserved.
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Programmer’s Reference 4.17 PCI controller The PCI controller is implemented in the FPGA and controls the interface to the PCI bus. Caution The PCI controller is provided by Xilinx. The source HDL for this device is not provided on the CD. The PCI controller will be deleted if you rebuild the FPGA image.
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Programmer’s Reference The PCI slave bridge connected to AHB M2 recognizes addresses 0x41000000 to 0x6FFFFFFF as being intended for a target within the PCI address space of the memory map, and passes accesses within this region to the PCI bus. The PCI master bridge connected to the PCI bus passes accesses to the AHB S bus. There are windows that provide access from the AHB M2 bus to the PCI expansion bus are listed in Table 4-49. Table 4-49 PCI bus memory map for AHB M2 bridge 4.17.
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Programmer’s Reference Table 4-50 PCI controller registers (continued) Address Name Access Description 0x10001010 PCI_FLAGS R/W Master and target abort flags. 0x10001014 PCI_SMAP0 R/W Translate PCI base address region 0 to AHB address. 0x10001018 PCI_SMAP1 R/W Translate PCI base address region 1 to AHB address. 0x1000101C PCI_SMAP2 R/W Translate PCI base address region 2 to AHB address.
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Programmer’s Reference Table 4-51 PCI_IMAPx register format Bits Description [31:4] Reserved. Use read-modify-write to preserve value. [3:0] Contains the value to use for bits [31:28] of the PCI address for accesses to this region. PCI_SELFID register Writing the slot location of the PB926EJ-S into this register enables normal configuration accesses to return information on the PB926EJ-S.
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Programmer’s Reference Figure 4-27 PCI_FLAGS register Table 4-53 PCI_FLAGS register format Bits Description [31:2] Reserved. [1] Target abort flag. The bit value is the same as bit 38 of the Command Status Register in the Xilinx PCI controller. This bit position is reserved for future use. [0] Master abort flag. The bit value is the same as bit 39 of the Command Status Register in the Xilinx PCI controller. This bit will be HIGH if an error occurred while the PB926EJ-S was operating as a master.
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Programmer’s Reference Figure 4-28 PCI to AHB S mapping The map register format is shown in Figure 4-29 and Table 4-54. Figure 4-29 PCI_SMAPx register Table 4-54 PCI_SMAPx register format 4.17.2 Bits Description [31:4] Reserved. Use read-modify-write to preserve value. [3:0] Contains the value to use for bits [31:28] of the AHB address when the PCI accesses the slave port.
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Programmer’s Reference Locating the self-config header table The slot positions for PCI cards are numbered from 11 to 31. The numbering is based on the address bit that is connected to the IDSEL line.
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Programmer’s Reference The contents of the PCI configuration header is listed in Table 4-57. The default values refer to the PB926EJ-S. Table 4-57 PCI configuration space header Address offset Configuration word function Default value +0x00 Device ID Vendor ID 0x030010EE +0x04 Status Command 0x02200000 +0x08 Class Code Rev ID 0x0B400000 +0x0C BIST (Reserved in PB926EJ-S) Header Type Lat.
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Programmer’s Reference Configuring the PCI interface To configure a PCI card in the expansion bus, first find the memory location that maps the PB926EJ-S into the system: 1. Scan addresses 0x41000000 + (n<<11) to locate the PCI slot holding the PB926EJ-S. The slot range for n is 11 to 31. If you are using the horizontal slot on the PCI expansion backplane, n is 29. 2. Write the value of n that indicates the slot position into the PCI_SELFID register. 3.
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Programmer’s Reference Limitations of the PCI interface The following limitations apply to the PCI interface present on the PB926EJ-S: • The interface is 32-bit only. • 0-bit, 24-bit and unaligned 16-bit transfers are not supported. • The initiator creates only single reads and writes. This is quite inefficient and results in low performance. It does, however, simplify the logic in the FPGA and allows 66MHz performance. • The target issues a retry response for reads until the data is ready.
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Programmer’s Reference Table 4-58 PCI bus commands supported 4-84 Command code Name Supported on target Supported on initiator b0000 Interrupt Acknowledge Ignored Not available b0001 Special Cycle Ignored Not available b0010 I/O read Yes Yes b0011 I/O write Yes Yes b0100 Reserved Ignored Not available b0101 Reserved Ignored Not available b0110 Memory Read Yes Yes b0111 Memory Write Yes Yes b1000 Reserved Ignored Not available b1001 Reserved Ignored Not available
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Programmer’s Reference 4.18 Real Time Clock, RTC The PrimeCell Real Time Clock Controller (RTC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. A counter in the RTC is incremented every second. The RTC can therefore be used as a basic alarm function or long time-base counter. The current value of the clock can be read at any time or the RTC can be programmed to generate an interrupt after counting for a programmed number of seconds.
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Programmer’s Reference 4.19 Serial bus interface A serial bus interface is implemented in the FPGA. The registers shown in Table 4-61 control the serial bus and provides access to control signals on the two memory expansion boards and to the time-of-year clock.
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Programmer’s Reference Software must manipulate the SCL and SDA bits directly to access the data in the three devices. The pre-defined eight-bit device addresses are listed in Table 4-62. See the \firmware\examples directory on the CD for example code for reading the memory expansion EEPROM.
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Programmer’s Reference 4.20 Smart Card Interface, SCI The PrimeCell Smart Card Interface (SCI) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. Table 4-63 SCI implementation Property Value Location ARM926EJ-S PXP Development Chip SCI0FPGA SCI1. Memory base address 0x101F0000 for SCI0 0x1000A000 for SCI1. Interrupt 15 on the primary controller (SCI0) 5 on the secondary controller (SCI1).
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Programmer’s Reference 4.21 Synchronous Serial Port, SSP The PrimeCell Synchronous Serial Port (SSP) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.
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Programmer’s Reference Note Use the SYS_CLCD register to control the SSP chip selects. See CLCD Control Register, SYS_CLCD on page 4-32. 4-90 • An offboard SSP device, such as an EEPROM, can be connected to expansion header J29. If you connect both the LCD adaptor board and the off board SSP device at the same time, ensure the correct SSP interface protocol is used when communicating with each device.
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Programmer’s Reference 4.22 Synchronous Static Memory Controller, SSMC The PrimeCell Synchronous Static Memory Controller (SSMC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.
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Programmer’s Reference 4.22.1 Register values Table 4-66 to Table 4-69 on page 4-93 lists the register values for the SSMC for typical operation of static memory devices and with a 35MHz system clock. Note The platform.a library contains memory setup routines. See Building an application with the platform library on page 2-23.
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Programmer’s Reference Table 4-68 Register values for Samsung SRAM Address Name of SSMC register Value Description +0x40 SMBIDCYR2 0x0 Idle Cycle Control Register for bank 2 +0x44 SMBWSTRDR2 0x2 Read Wait State Control Reg bank 2 +0x48 SMBWSTWRR2 0x2 Write Wait State Control Reg Bank 2 +0x4c SMBWSTOENR2 0x0 Output Enable Assertion Delay 2 +0x50 SMBWSTWENR2 0x1 Write Enable Assertion Delay 2 +0x54 SMBCR2 0x303021 Control Register for memory bank 2 +0x5c SMBWSTBRDR2 0x0 Burst R
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Programmer’s Reference Table 4-70 Register values for Spansion LV256 (continued) 4-94 Address Name of SSMC register Value Description +0x8c SMBWSTOENR4 0x1 Output Enable Assertion Delay 4 +0x90 SMBWSTWENR4 0x1 Write Enable Assertion Delay 4 +0x94 SMBCR4 0x303121 Control Register for memory bank 4 +0x9c SMBWSTBRDR4 0x1 Burst Read Wait state Control Reg 4 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Programmer’s Reference 4.23 System Controller The ARM PrimeXsys System Controller is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. Table 4-71 System controller implementation Property Value Location ARM926EJ-S PXP Development Chip Memory base address 0x101E0000 Interrupt NA DMA NA Release version ARM SYSCTRL SP810 r0p0-00ltd0 Reference documentation ARM PrimeCell System Controller (SP810) Technical Reference Manual.
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Programmer’s Reference 4.24 Timers The Dual-Timer module is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. There are two Dual-Timer modules present in the ARM926EJ-S PXP Development Chip. Table 4-72 Timer implementation Property Value Location ARM926EJ-S PXP Development Chip Memory base address 0x101E2000 for Timer 0 0x101E2020 for Timer 1 0x101E3000 for Timer 2 0x101E3020 for Timer 3.
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Programmer’s Reference 4.25 UART The PrimeCell UART is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. There are three UARTs in the ARM926EJ-S PXP Development Chip and one UART is in FPGA. The 24MHz reference clock to the UARTs come from the crystal oscillator that is part of OSC0.
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Programmer’s Reference 4.25.1 PrimeCell Modifications The PrimeCell UART varies from the industry-standard 16C550 UART device as follows: • receive FIFO trigger levels are 1/8, 1/4, 1/2, 3/4, and 7/8 • the internal register map address space, and the bit function of each register differ • the deltas of the modem status signals are not available. • 1.5 stop bits not available (1 or 2 stop bits only are supported) • no independent receive clock. 4-98 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Programmer’s Reference 4.26 USB interface The USB interface is provided by an OTG243 controller that provides a standard USB host controller and an On-The-Go (OTG) dual role device controller. The USB host has one or two downstream ports. The OTG can function as either a host or slave device.
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Programmer’s Reference 4.27 Vector Floating Point, VFP9 The VFP9-S coprocessor is an implementation of the Vector Floating-point Architecture version 2 (VFPv2). It provides low-cost floating-point computation that is fully compliant with the ANSI/IEEE Std. 754-1985, IEEE Standard for Binary Floating-Point Arithmetic. The VFP9-S coprocessor supports all addressing modes described in section 5 of the ARM Architecture Reference Manual.
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Programmer’s Reference 4.28 Watchdog The PrimeCell Watchdog module is an AMBA compliant SoC peripheral developed, tested and licensed by ARM Limited. The Watchdog module consists of a 32-bit down counter with a programmable timeout interval that has the capability to generate an interrupt and a reset signal on timing out. It is intended to be used to apply a reset to a system in the event of a software failure. Note The Watchdog counter is disabled if the core is in debug state.
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Appendix A Signal Descriptions This appendix provides a summary of signals present on the PB926EJ-S connectors.
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Signal Descriptions A.1 Synchronous Serial Port interface Figure A-1 shows the signals on the expansion SSP interface connector J29. Figure A-1 SSP expansion interface The signals associated with the SSP are shown in Table A-1.
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Signal Descriptions A.2 Smart Card interface The PB926EJ-S contains two Smart Card SIM sockets: • J48 for SIM 0 (J25 uses an alternate layout for SIM 0 and is not fitted) • J49 for SIM1 (J26 uses an alternate layout for SIM 0 and is not fitted). Sockets J48 and J49 include a switch for card detection. The signals on the SIM sockets are also connected to the SCI expansion socket. The signals associated with the SCI are shown in Table A-2.
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Signal Descriptions Figure A-3 shows the pinout of the connector J28. This can be used to connect to an off-PCB smart card device. Figure A-3 J28 SCI expansion Table A-3 lists the signals on the SCI expansion connector.
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Signal Descriptions A.3 UART interface The PB926EJ-S provides four serial transceivers. Figure A-4 shows the pin numbering for the 9-pin D-type male connector used on the PB926EJ-S and Table A-4 shows the signal assignment for the connectors. The pinout shown in Figure A-4 is configured as a Data Communications Equipment (DCE) device.
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Signal Descriptions A.4 USB interface USB2 and USB3 provide USB host interfaces and connect through the type A connector J7. USB1 provides an OTG interface and connects through the OTG connector J6. Note For a full description of the USB signals refer to the datasheet for the TransDimension OTG243. Figure A-5 shows the USB connectors. Figure A-5 USB interfaces A-6 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Signal Descriptions A.5 Audio CODEC interface The PB926EJ-S provides three jack connectors that enable you to connect to the microphone and auxiliary inputs, and line level output on the CODEC. Figure A-6 shows the pinouts of the sockets. Note A link on the board enables bias voltage to be applied to the microphone (see Advanced Audio Codec Interface, AACI on page 3-56).
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Signal Descriptions A.6 MMC and SD flash card interface The MMC/SD card sockets provides nine pins that connect to the card when it is inserted into the socket. Figure A-7 shows the pin numbering and signal assignment. In addition, the socket contains switches that are operated by card insertion and provide signaling on the CARDINx and MCI_WPROT signals.
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Signal Descriptions Table A-5 lists the signal assignments.
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Signal Descriptions A.7 CLCD display interface The CLCD interface adaptor board connector (J18) is shown in Figure A-9 on page A-12. The connectorsignals are listed in Table A-6. See Appendix C CLCD Display and Adaptor Board for details on the CLCD adaptor board. See CLCDC interface on page 3-61 for details on CLCD signals.
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Signal Descriptions Table A-6 CLCD Interface board connector J18 (continued) Pin Signal Pin Signal 22 TSnSS 56 LCDID2 23 TSMISO 57 LCDID3 24 TSMOSI 58 LCDID4 25 LCDXWR 59 GND 26 LCDSD0 60 GND 27 LCDXRD 61 GND 28 LCDXCS 62 3V3 29 LCDDATnCOM 63 3V3 30 LCDSD0OUTnIN 64 5V 31 CLPOWER 65 5V 32 nLCDIOON 66 VLCD 33 PWR3V5VSWITCH 67 VLCD 34 VDDPOSSWITCH 68 VDDNEGSWITCH Note The R[7:0], G[7:0], and B[7:0] signals are digital CLCD signals.
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Signal Descriptions B0 B2 B4 B6 G0 G2 G4 G6 R0 R2 R4 R6 CLLE CLAC CLCP CLLP CLFP TSnKPADIRQ TSnPENIRQ TSnDAV TSSCLK TSnSS TSMISO TSMOSI LCDXWR LCDSD0 LCDXRD XCDXCS LCDDATnCOMM LCDSD0OUTnIN CLPOWER nLCDIOON PWR3V5VSWITCH VDDPOSSWITCH 1 35 34 68 B1 B3 B5 B7 G1 G3 G5 G7 R1 R3 R5 R7 GND GND GND GND GND GND GND LCDID0 LCDID1 LCDID2 LCDID3 LCDID4 GND GND GND 3V3 3V3 5V 5V VLCD VLCD VDDNEGSWITCH Figure A-9 CLCD Interface connector J18 A-12 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Signal Descriptions A.8 VGA display interface The VGA connector (J19) is shown in Figure A-10. The connector signals are listed in Table A-7. A Digital to Analog Converter (DAC) converts the digital CLCD data and synchronization signals into the analogue VGA signals.
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Signal Descriptions A.9 GPIO interface Four eight-bit General Purpose Input/Output (GPIO) controllers are incorporated into the ARM926EJ-S PXP Development Chip. The signals on the GPIO connector are shown in Figure A-11.
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Signal Descriptions A.10 Keyboard and mouse interface The pinout of the KMI connectors J23 and J24 is shown in Figure A-12. 6 5 4 3 2 1 Figure A-12 KMI connector Table A-8 shows signals on the KMI connectors.
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Signal Descriptions A.11 Ethernet interface The RJ45 Ethernet connector J5 is shown in Figure A-13. LEDA (green) and LEDB (yellow) are connected to the LAN91C111 controller. The function of the LEDs is determined by registers in the controller. Typical usage would be to monitor transmit activity and packet detection. Pin 1 LEDA LEDB Figure A-13 Ethernet connector J5 The signals on the Ethernet cable are shown in Table A-9. Table A-9 Ethernet signals A-16 Copyright © 2003-2010 ARM Limited.
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Signal Descriptions A.12 RealView Logic Tile header connectors Figure A-14 shows the pin numbers and power-blade usage of the HDRX, HDRY, and HDRZ headers on the PB926EJ-S. Figure A-14 HDRX, HDRY, and HDRZ (upper) pin numbering Caution The I/O voltage on some pins of RealView Logic Tiles can be programmed by changing resistors on the tile. Signals between RealView Logic Tiles can be altered safely if both the sending and receiving tile use the same voltage.
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Signal Descriptions A.12.1 HDRX signals Table A-10 describes the signals on the HDRX (J9) pins. Note The tile signal names refer to the signal present on the upper side of a RealView Logic Tile. That is, the headers on the PB926EJ-S correspond to the upper headers of a tile. The naming convention simplifies designs that might mount on top of either the PB926EJ-S or a RealView Logic Tile.
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Signal Descriptions Table A-10 HDRX (J9) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal AHBMONITOR12 XU72 36 35 XU107 HADDRM2_11 AHBMONITOR11 XU71 38 37 XU108 HADDRM2_12 AHBMONITOR10 XU70 40 39 XU109 HADDRM2_13 AHBMONITOR9 XU69 42 41 XU110 HADDRM2_14 AHBMONITOR8 XU68 44 43 XU111 HADDRM2_15 AHBMONITOR7 XU67 46 45 XU112 HADDRM2_16 AHBMONITOR6 XU66 48 47 XU113 HADDRM2_17 AHBMONITOR5 XU65 50 49 XU114 HADDRM2_18 AHBMONITO
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Signal Descriptions Table A-10 HDRX (J9) signals (continued) A-20 Platform signal Tile signal Pin Pin Tile signal Platform signal HBUSREQM2 XU48 84 83 XU131 HCLKM1DRVL2S HWRITEM2 XU47 86 85 XU132 HCLKM2DRVL2S HBURSTM2_2 XU46 88 87 XU133 HCLKSDRVL2S HBURSTM2_1 XU45 90 89 XU134 F2LSPARE0 HBURSTM2_0 XU44 92 91 XU135 F2LSPARE1 HPROTM2_3 XU43 94 93 XU136 F2LSPARE2 HPROTM2_2 XU42 96 95 XU137 F2LSPARE3 HPROTM2_1 XU41 98 97 XU138 NC HPROTM2_0 XU40 100 99
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Signal Descriptions Table A-10 HDRX (J9) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal GP3_0 XU24 132 131 XU155 HDATAM2_7 GP2_7 XU23 134 133 XU156 HDATAM2_8 GP2_6 XU22 136 135 XU157 HDATAM2_9 GP2_5 XU21 138 137 XU158 HDATAM2_10 GP2_4 XU20 140 139 XU159 HDATAM2_11 GP2_3 XU19 142 141 XU160 HDATAM2_12 GP2_2 XU18 144 143 XU161 HDATAM2_13 GP2_1 XU17 146 145 XU162 HDATAM2_14 GP2_0 XU16 148 147 XU163 HDATAM2_15 GP1_7
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Signal Descriptions Table A-10 HDRX (J9) signals (continued) A.12.2 Platform signal Tile signal Pin Pin Tile signal Platform signal GP0_2 XU2 176 175 XU177 HDATAM2_29 GP0_1 XU1 178 177 XU178 HDATAM2_30 GP0_0 XU0 180 179 XU179 HDATAM2_31 HDRY signals Table A-11 describes the signals on the HDRY (J12) pins. The tile signal names refer to the signal present on the upper side of a RealView Logic Tile.
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Signal Descriptions Table A-11 HDRY (J12) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal HADDRS9 YU105 32 31 YU74 UART0TXD HADDRS10 YU106 34 33 YU73 SIRIN0 HADDRS11 YU107 36 35 YU72 nSIROUT0 HADDRS12 YU108 38 37 YU71 nUART1CTS HADDRS13 YU109 40 39 YU70 UART1RXD HADDRS14 YU110 42 41 YU69 nUART1RTS HADDRS15 YU111 44 43 YU68 UART1TXD HADDRS16 YU112 46 45 YU67 nUART2CTS HADDRS17 YU113 48 47 YU66 UART2RXD HADDRS18
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Signal Descriptions Table A-11 HDRY (J12) signals (continued) A-24 Platform signal Tile signal Pin Pin Tile signal Platform signal SSPFSSIN YU129 80 79 YU50 HRESPS0 SSPRXD YU130 82 81 YU49 HREADYS SSPCLKOUT YU131 84 83 YU48 HMASTLOCKS SSPFSSOUT YU132 86 85 YU47 HSELS SSPTXD YU133 88 87 YU46 HBURSTS2 nSSPCTLOE YU134 90 89 YU45 HBURSTS1 nSSPOE YU135 92 91 YU44 HBURSTS0 LT_CLCD_SPARE0 YU136 94 93 YU43 HPROTS3 LT_CLCD_SPARE1 YU137 96 95 YU42 HPROTS2
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Signal Descriptions Table A-11 HDRY (J12) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal HDATAS5 YU153 128 127 YU26 LT_CLCP HDATAS6 YU154 130 129 YU25 LT_CLLE HDATAS7 YU155 132 131 YU24 LT_CLLP HDATAS8 YU156 134 133 YU23 LT_CLCD_B7 HDATAS9 YU157 136 135 YU22 LT_CLCD_B6 HDATAS10 YU158 138 137 YU21 LT_CLCD_B5 HDATAS11 YU159 140 139 YU20 LT_CLCD_B4 HDATAS12 YU160 142 141 YU19 LT_CLCD_B3 HDATAS13 YU161 144 143 YU18
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Signal Descriptions Table A-11 HDRY (J12) signals (continued) A.12.3 Platform signal Tile signal Pin Pin Tile signal Platform signal HDATAS29 YU177 176 175 YU2 LT_CLCD_R2 HDATAS30 YU178 178 177 YU1 LT_CLCD_R1 HDATAS31 YU179 180 179 YU0 LT_CLCD_R0 HDRZ The tile signal names refer to the signal present on the upper side of a RealView Logic Tile. The HDRZ plug and socket have slightly different pinouts. Table A-12 describes the signals on the HDRZ (J8) pins.
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Signal Descriptions Table A-12 HDRZ (J8) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal NC ZU240 32 31 ZU143 EXP_SMADDR15 NC ZU239 34 33 ZU144 EXP_SMADDR16 NC ZU238 36 35 ZU145 EXP_SMADDR17 NC ZU237 38 37 ZU146 EXP_SMADDR18 NC ZU236 40 39 ZU147 EXP_SMADDR19 NC ZU235 42 41 ZU148 EXP_SMADDR20 NC ZU234 44 43 ZU149 EXP_SMADDR21 NC ZU233 46 45 ZU150 EXP_SMADDR22 NC ZU232 48 47 ZU151 EXP_SMADDR23 NC ZU231 50 49 Z
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Signal Descriptions Table A-12 HDRZ (J8) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal VICINTSOURCE30 ZU215 82 81 ZU168 EXP_nEXPCS VICINTSOURCE29 ZU214 84 83 ZU169 DMACBREQ0 VICINTSOURCE28 ZU213 86 85 ZU170 DMACBREQ1 VICINTSOURCE27 ZU212 88 87 ZU171 DMACBREQ2 VICINTSOURCE26 ZU211 90 89 ZU172 DMACBREQ3 VICINTSOURCE25 ZU210 92 91 ZU173 DMACBREQ4 VICINTSOURCE24 ZU209 94 93 ZU174 DMACBREQ5 VICINTSOURCE23 ZU208 96 95 ZU175
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Signal Descriptions Table A-12 HDRZ (J8) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal NC CLK_NEG_DN_IN 132 131 D_nTRST nTRST HCLKM1RESF2L CLK_POS_UP_OUT 134 133 D_TDO_IN D_TDO_OUT HCLKSRESF2L CLK_NEG_UP_OUT 136 135 D_TDI TDI NC CLK_UP_THRU 138 137 D_TCK_OUT D_TCK_IN LT_SMCLK0 CLK_OUT_PLUS1 140 139 D_TMS_OUT D_TMS_IN LT_SMCLK1 CLK_OUT_PLUS2 142 141 D_RTCK SDC_TCK NC CLK_IN_PLUS2 144 143 C_nSRST nSRST NC CLK_IN_PLUS1 146
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Signal Descriptions Table A-12 HDRZ (J8) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal EXP_SMDATAS1 Z65 176 175 Z62 EXP_nSMWEN EXP_SMDATAS2 Z66 178 177 Z61 NC EXP_SMDATAS3 Z67 180 179 Z60 NC EXP_SMDATAS4 Z68 182 181 Z59 NC EXP_SMDATAS5 Z69 184 183 Z58 NC EXP_SMDATAS6 Z70 186 185 Z57 NC EXP_SMDATAS7 Z71 188 187 Z56 NC EXP_SMDATAS8 Z72 190 189 Z55 NC EXP_SMDATAS9 Z73 192 191 Z54 NC EXP_SMDATAS10 Z74 194 193
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Signal Descriptions Table A-12 HDRZ (J8) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal EXP_SMDATAS26 Z90 226 225 Z37 HBURSTM1_0 EXP_SMDATAS27 Z91 228 227 Z36 HPROTM1_3 EXP_SMDATAS28 Z92 230 229 Z35 HSIZEM1_1 EXP_SMDATAS29 Z93 232 231 Z34 HSIZEM1_0 EXP_SMDATAS30 Z94 234 233 Z33 HTRANSM1_1 EXP_SMDATAS31 Z95 236 235 Z32 HTRANSM1_0 HADDRM1_0 Z96 238 237 Z31 HDATAM1_31 HADDRM1_1 Z97 240 239 Z30 HDATAM1_30 HADDRM1_2 Z98
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Signal Descriptions Table A-12 HDRZ (J8) signals (continued) Platform signal Tile signal Pin Pin Tile signal Platform signal HADDRM1_19 Z115 276 275 Z12 HDATAM1_12 HADDRM1_20 Z116 278 277 Z11 HDATAM1_11 HADDRM1_21 Z117 280 279 Z10 HDATAM1_10 HADDRM1_22 Z118 282 281 Z9 HDATAM1_9 HADDRM1_23 Z119 284 283 Z8 HDATAM1_8 HADDRM1_24 Z120 286 285 Z7 HDATAM1_7 HADDRM1_25 Z121 288 287 Z6 HDATAM1_6 HADDRM1_26 Z122 290 289 Z5 HDATAM1_5 HADDRM1_27 Z123 292 291 Z4
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Signal Descriptions A.13 Test and debug connections The PB926EJ-S provides test points, ground points, and connectors to aid diagnostics as shown in Figure A-15. Figure A-15 Test points and debug connectors ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Signal Descriptions This section contains the following subsections: • Overview of test points • JTAG on page A-36 • USB debug port on page A-36 • Trace connector pinout on page A-37 • Embedded logic analyzer on page A-38 • AHB monitor on page A-38 • FPGA debug connector pinout on page A-40. A.13.1 Overview of test points The functions of the test points on the PB926EJ-S are summarized in Table A-13.
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Signal Descriptions Table A-13 Test point functions (continued) Test point Signal Function TP15 1V8 1.
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Signal Descriptions A.13.2 JTAG Figure A-16 shows the pinout of the JTAG connector J31 and Table 3-25 on page 3-98 provides a description of the JTAG and related signals. All JTAG active HIGH input signals have pull-up resistors (DGBRQ is active LOW and has a pull-down resistor). Note The term JTAG equipment refers to any hardware that can drive the JTAG signals to devices in the scan chain.
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Signal Descriptions A.13.4 Trace connector pinout Table A-14 lists the pinout of the trace connector J14. The Mictor connector is shown in Figure A-19 on page A-38.
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Signal Descriptions A.13.5 Embedded logic analyzer Figure A-18 shows the signals on the embedded logic analyzer connector J33. Use an embedded logic analyzer to debug FPGA designs and software at the same time. For more information, see the documentation supplied with your analyzer. (The ChipScope product is described on the Xilinx web site at www.xilinx.com.
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Signal Descriptions Table A-15 AHB monitor connector J17 ARM DUI 0224I Channel Pin Pin Channel Not connected 1 2 Not connected Not connected 3 4 Not connected AHBMONITOR32 5 6 AHBMONCLK0 AHBMONITOR31 7 8 AHBMONITOR15 AHBMONITOR30 9 10 AHBMONITOR14 AHBMONITOR29 11 12 AHBMONITOR13 AHBMONITOR28 13 14 AHBMONITOR12 AHBMONITOR27 15 16 AHBMONITOR11 AHBMONITOR26 17 18 AHBMONITOR10 AHBMONITOR25 19 20 AHBMONITOR9 AHBMONITOR24 21 22 AHBMONITOR8 AHBMONITOR23 23 24 A
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Signal Descriptions A.13.7 FPGA debug connector pinout The FPGA debug connector contains address and decode signals that the FPGA generates to communicate with the USB and Ethernet controllers. Table A-16 lists the pinout of the FPGA debug connector. The Mictor connector is shown in Figure A-19 on page A-38.
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Appendix B Specifications This appendix contains the specification for the PB926EJ-S. It contains the following sections: • Electrical specification on page B-2 • Clock rate restrictions on page B-5 • Mechanical details on page B-9. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Specifications B.1 Electrical specification This section provides details of the voltage and current characteristics for the PB926EJ-S. B.1.1 Bus interface characteristics Table B-1 shows the PB926EJ-S electrical characteristics. Table B-1 PB926EJ-S electrical characteristics B-2 Symbol Description Min Max Unit DC IN DC input voltage 9 15 V 12V Supply voltage from terminal or PCI 11.4 12.6 V 3V3 Supply voltage (interface signals) 3.1 3.5 V 5V Supply voltage 4.75 5.
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Specifications B.1.2 Current requirements This section lists the current requirements of the PB926EJ-S. Powered from DC IN Table B-2 shows the current requirements at room temperature and nominal voltage powered from the DC IN connector. These measurements include the current drawn by Multi-ICE, approximately 160mA at 3.3V. Table B-2 Current requirements from DC IN (12V) System DC IN typical DC IN max Standalone 0.
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Specifications Loading on supply voltage rails Table B-4 lists the maximum current load that can be placed on the supply voltage rails. Table B-4 Maximum current load on supply voltage rails System 3.3V 5V 5V Supplied from DC IN (12V at 3A) 2 1.5A 3A Supplied from J34 or PCI (12V at 3A, 5V at 3A, and 3.
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Specifications B.2 Clock rate restrictions The default clock rates for reliable operation are: CPUCLK 210MHz MPMCCLK 70MHz HCLK 70MHz HCLKEXT 35MHz MBXCLK 70MHz SMCLK 50MHz If you have added one or more RealView Logic Tiles, you might need to reduce these clock rates. For timing on the buses and peripherals, see: • AHB bus timing on page B-6 • Memory timing on page B-7 • Peripheral timing on page B-7.
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Specifications B.2.1 AHB bus timing Table B-5 lists the timing for the AHB buses. (The bus clock frequency is typically 35MHz for a tcyc of 28.5ns).
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Specifications B.2.2 Memory timing Table B-6 shows the memory timing. For more detail on timing and example waveforms, see the ARM PrimeCell Static Memory Controller (PL093) Technical Reference Manual and the ARM PrimeCell Multiport Memory Controller (GX175) Technical Reference Manual.
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Specifications Table B-7 Peripherals and controller timing Peripheral signals Clock tov toh tis tih CLCDC outputs (CLD[23:0], CLPOWER, CLLP, CLCP, CLFP, CLAC, and CLLE) The maximum frequency of CLCDCLK is 100MHz for a tcyc of 10ns. CLCDCLK 12.5ns -2.5ns - - SCI outputs (nSCICLKOUTEN, SCICLKOUT, nSCIDATAOUTEN, nSCICLKEN, and nSCIDATAEN) SCIREFCLK 14ns -1ns - - SCI inputs (SCICLKIN, SCIDATAIN, and SCIDETECT) The maximum frequency of SCIREFCLK is 100MHz for a tcyc of 10ns.
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Specifications B.3 Mechanical details Figure B-1 shows the mechanical outline of the PB926EJ-S. Figure B-1 Baseboard mechanical details ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Appendix C CLCD Display and Adaptor Board This appendix describes the external CLCD adaptor board and display. It contains the following sections: • About the CLCD display and adaptor board on page C-2 • Installing the CLCD display on page C-6 • LCD power control on page C-7 • Touchscreen controller interface on page C-11 • Connectors on page C-15 • Mechanical layout on page C-19. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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CLCD Display and Adaptor Board C.1 About the CLCD display and adaptor board The CLCD interface board provides multiple sockets for different types of CLCD displays and touchscreens. It connects to the PB926EJ-S by a single cable.
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CLCD Display and Adaptor Board Six pushbutton switches are mounted on the interface board below the 2.2 or 3.8 inch display. The state of the switches can be read from the touchscreen controller interface. The touchscreen interface on the CLCD interface board is described in Touchscreen controller interface on page C-11. The selftest program supplied on the CD reads the position of a pen on the touchscreen and displays it on the CLCD or VGA display connected to the board. The 2.2 and 3.
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CLCD Display and Adaptor Board Figure C-3 Large CLCD enclosure The 2.2 and 3.8 inch CLCD displays are mounted on the top side of the adaptor board as shown in Figure C-4 on page C-5. C-4 Copyright © 2003-2010 ARM Limited. All rights reserved.
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CLCD Display and Adaptor Board C.2 Installing the CLCD display To install the CLCD display: 1. Connect one end of the CLCD expansion cable to the CLCD adaptor board. 2. Connect the other end of the cable to the PB926EJ-S CLCD expansion connector on the enclosure. 3. If required, program the CLCD control registers SYS_CLCD and SYS_CLCDSER to sequence the power to the LCD display and specify the bit format. See the CLCDC interface on page 3-61.
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CLCD Display and Adaptor Board C.2.1 Configuration The CLCD adaptor board contains factory-installed links that identify the type of display. The display matching the identification links settings are listed in Table C-1. The value of the bits CLCDID[4:0] in the SYS_CLCD register can be read from software to determine the display in use with the board. Table C-1 Displays available with adaptor board C.2.2 Backlight inverter Touchscreen Display Sanyo TM38QV67A02A TDK CXA-0341 Part of display 3.
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CLCD Display and Adaptor Board SWITCHED_VDD_NEG This –5V to –28V supply is generated from 5V. It can be enabled by VDDNEGSWITCH in SYS_CLCD or permanently enabled by link 14. SWITCHED_VDD_POS This 11V to 28V supply is generated from 5V. It can be controlled by the touchscreen D/A converter or manually with a pot. It can be enabled by VDDPOSSWITCH in SYS_CLCD or permanently enabled by link 11. This supply is used to generate the STN bias voltage.
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CLCD Display and Adaptor Board Table C-2 shows the power configuration for the three displays. For additional information on configuring the CLCD displays, see the selftest code provided on the CD. Table C-2 Power configuration Voltage control Epson 2.2” Sanyo 3.8” Sharp 8.4” Buffer IO SWITCHED_FIXED CLPOWER CLPOWER SWITCHED_VDD_POS Software control 15V Software control SWITCHED_VDD_NEG –10V –10V –10V CLPOWER 2.85V 3.3V 3.3V FIXED_SWITCH 1.8V 5V 5V INV_IO 5V 3.
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CLCD Display and Adaptor Board Buffered sync signals (BUF_CLLE, BUF_CLLP, BUF_CLFP, BUF_CLAC, and BUF_CLCP) Sync signals (CLLE, CLLP, CLFP, CLAC, and CLCP) Buffers Buffered video signals (BUFR_R[7:0], BUFR_G[7:0], and BUFR_B[7:0] ) Video signals R[7:0], G[7:0], B[7:0] V+ SWITCHED_CLPWR Power CL SWITCHED_FIXED Link 13 SWITCHED_VDD_NEG Power VDD NEG Link 14 SWITCHED_VDD_POS Power VDD POS R25 (remove for fixed VDD_POS) DACOUT VIN Link 2 J13 AUX/Batt/keypad connector INV_IO VR4 BRIGHTNESS J12
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CLCD Display and Adaptor Board C.3 Touchscreen controller interface The touchscreen interface is designed to connect to a four-wire resistive touchscreen. It is driven by the TouchScreen controller TSC2200 and described in: • Touchscreen interface architecture • Touchscreen controller programmer’s interface on page C-13. The Selftest program supplied on the CD demonstrates how to communicate with the touchscreen controller.
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TSSCLK TSnDAV VBAT[2:1] AUX[2:1] TSnKPADIRQ TSnPENIRQ RGB and sync to display Power shutdown signals FB2 (DA out) R1 R2 R3 R4 S3 S4 S5 S6 S7 C1 C2 C3 C4 Power control VDD POS S8 J13 A/D and keypad connector Interface socket TSnSS X_POS Y_POS X_NEG Y_NEG J10 TSMOSI Touch screen controller J3 TSMISO J8 CLCD Display and Adaptor Board User switches Figure C-7 Touchscreen and keypad interface The connection between the resistive elements of the touchscreen and J3, J8, or J10 is shown in F
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CLCD Display and Adaptor Board C.3.2 Touchscreen controller programmer’s interface The LCD Touch Screen Controller Interface (TSCI) is based on a TSC2200 PDA analogue interface circuit. Use the ARM926EJ-S PXP Development Chip SSP interface to configure and read the touch screen. For information on the touch screen registers, see the TSC2200 data sheet. The TSC2200 also incorporates a sixteen key keypad interface and two 12bit analogue inputs that are available through the LCD expansion header J13.
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CLCD Display and Adaptor Board Example C-2 Configuring and reading the TSCI interface Configure the SSP interface Configure the TSCI registers Enable the touch screen pendown interrupt (on SIC) ... On touch screen pendown interrupts ... touch screen interrupt handler Enable the touch screen event timer (TIMER 1-4) for approx. 2mS intervals ... On touch screen timer events ...
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CLCD Display and Adaptor Board C.4 Connectors This section describes the connectors present on the CLCD adaptor board. For details of the connectors present on the PB926EJ-S, see Appendix A Signal Descriptions. C.4.1 Interface connector The signals on the CLCD interface connector J2 are shown in Table C-4.
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CLCD Display and Adaptor Board C.4.2 LCD prototyping connector The signals on the LCD prototyping connector J1 are shown in Table C-5.
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CLCD Display and Adaptor Board Table C-5 LCD prototyping connector J1 (continued) C.4.3 Signal Pin Pin Signal BUF_G0 45 46 LCD UP_DOWN BUF_G1 47 48 SWITCHED_VDD_POS SWITCHED_CLPWR 49 50 SWITCHED_VDD_NEG Touchscreen prototyping connector The signals on the touchscreen prototyping connector J3 are shown in Table C-6. Table C-6 Touchscreen prototyping connector J3 C.4.
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CLCD Display and Adaptor Board C.4.5 A/D and keypad connector The signals on the connector J13 are shown in Table C-7 on page C-17. This connector enables the connection of an external keypad (R[4:1] are the keypad row scan output signals and C[4:1] are the column detect input signals). There are also connections to the analog to digital converter inputs on the CLCD adaptor board (AUX[2:1] and VBAT[2:1]).
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CLCD Display and Adaptor Board C.5 Mechanical layout Shows the board layout and location of the CLCD, switches, and mounting holes. Figure C-9 CLCD adaptor board mechanical layout ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Appendix D PCI Backplane and Enclosure This appendix describes the PCI backplane and enclosure. It contains the following sections: • Connecting the PB926EJ-S to the PCI enclosure on page D-2 • Backplane hardware on page D-6 • Connectors on page D-10. For details on configuring the PCI controller and PCI expansion cards, see PCI controller on page 4-74. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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PCI Backplane and Enclosure D.1 Connecting the PB926EJ-S to the PCI enclosure This section describes how to configure the PCI backplane and connect the PB926EJ-S to the PCI enclosure. To use the PB926EJ-S with the PCI backplane and enclosure: 1. Configure the PB926EJ-S as described in Setting up the RealView Platform on page 2-2. Caution Do not connect power to the PB926EJ-S yet. 2. Connect Multi-ICE to the board, or use the USB debug port. See Connecting JTAG debugging equipment on page 2-8.
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PCI Backplane and Enclosure Caution Do not connect power to the screw terminals or to the power socket on the PB926EJ-S. 7. Execute the initialization code to setup the PCI address-mapping registers (see PCI controller on page 4-74) Figure D-1 Installing the platform board into the PCI enclosure ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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PCI Backplane and Enclosure D.1.1 Setting the backplane configuration switches There are four control switches on the PCI backplane board as shown in Figure D-3 on page D-6. The switches are arranged into two switch blocks, SW1 and SW2. SW1-1 and SW1-2 control clock rate: SW1-1 SW1-2 SW1-1 positions are labeled Manual and Auto and select between manual or automatic clock selection: • In Manual position, the clock is determined by the settings of the manual clock select switch SW1-2.
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PCI Backplane and Enclosure D.1.2 Connecting two PB926EJ-S boards Figure D-2 shows two PB926EJ-S boards and a VGA controller connected to the PCI backplane. The PCI controller in the top PB926EJ-S is operating as a PCI bus slave and the PCI controller in the bottom PB926EJ-S is operating as a PCI bus master. The VGA card is also operating as a slave. Figure D-2 Multiple boards on PCI bus Note You can only plug the PB926EJ-S into a PC PCI motherboard that uses 64-bit sockets (3.3V signal levels).
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PCI Backplane and Enclosure D.2 Backplane hardware The mechanical layout for the PCI backplane is shown in Figure D-3. 91mm 46mm 10mm 10mm TP2 18.3mm 20.3mm TP4 50.
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PCI Backplane and Enclosure The switches, indicators, and test points for the PCI backplane are listed in Table D-1, Table D-2 on page D-8, and Table D-3 on page D-8. Table D-1 LED indicators ARM DUI 0224I LED Signal Description 1 MAN1nMAN2 This LED illuminates to indicate Man2 clock selection 2 MANnAUTO This LED illuminates to indicate Auto clock selection 5 CLK33ACTIVE This LED illuminates to indicate 33MHz bus speed. 6 CLK66ACTIVE This LED illuminates to indicate 66MHz bus speed.
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PCI Backplane and Enclosure Table D-2 Configuration switches Switch Signal Description SW1-1 MAN1nMAN2 Determines the clock rate when SW1[1] is in the Manual position. See Setting the backplane configuration switches on page D-4. SW1-2 MANnAUTO Selects between manual (ON) or automatic (OFF) clock selection SW2-1 nINCPLD Omits (ON) or includes (OFF) the PLD in the scan chain. SW2-2 TESTnEN Omits (ON) or includes (OFF) the PCI sockets in the scan chain.
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PCI Backplane and Enclosure D.2.1 JTAG signals The JTAG signal flow is shown in Figure D-4. Note The JTAG chain on the PCI expansion board is independent of the JTAG chain on the PB926EJ-S. Figure D-4 JTAG signal flow on the PCI backplane ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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PCI Backplane and Enclosure D.3 Connectors This section describes the connectors present on the PCI backplane. D.3.1 Power connector The power connector is a standard ATX style connector as used in PCs. The pinout for the connector is listed in Table D-5.
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PCI Backplane and Enclosure D.3.2 Logic analyzer connector Figure D-5 and Table D-6 show the pinout of the Mictor connector J4. You can use this connector to monitor PCI signals on the backplane. Note Agilent (formerly HP) and Tektronix label these connectors differently, but the assignments of signals to physical pins is appropriate for both systems and pin 1 is always in the same place.
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PCI Backplane and Enclosure Table D-6 Mictor connector pinout (continued) D.3.3 Channel Pin Pin Channel PCI_nREQB 27 28 PCI_nRST PCI_nREQA 29 30 PCI_nSTOP SPARE4 31 32 PCI_nDEVSEL SPARE3 33 34 PCI_nFRAME SPARE2 35 36 PCI_nLOCK SPARE1 37 38 PCI_PAR JTAG connector The signals on the JTAG connector J5 are shown in Figure D-6.
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Appendix E Memory Expansion Boards This appendix describes expansion memory modules for the PB926EJ-S. It contains the following sections: • About memory expansion on page E-2 • Fitting a memory board on page E-5 • EEPROM contents on page E-6 • Connector pinout on page E-13 • Mechanical layout on page E-20. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Memory Expansion Boards E.1 About memory expansion You can fit static and dynamic memory expansion boards to the PB926EJ-S: • There are five chip select signals available on the static expansion board. Each of these can select 64MB of SRAM. • There are 3 chip select signals available on the dynamic expansion board. Each of these can select 128MB of SDRAM. The block diagrams for typical memory boards are shown in Figure E-1 and Figure E-2 on page E-3.
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Memory Expansion Boards SMDATA[31:0] SMAADD[25:0] and control signals Static memory EXPnCS (CS3) Chip select links Expansion connector CS[7:4] 3V3 CSWIDTH1 CSWIDTH0 CSWIDTH select link GND SBSCL SBSDA E2PROM Figure E-2 Static memory board block diagram E.1.1 Operation without expansion memory You can operate the PB926EJ-S without a memory expansion board because it has 2MB of SSRAM, 128MB SDRAM, 64MB NOR flash, and 64MB NAND flash permanently fitted.
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Memory Expansion Boards Memory width selection on the static memory board The memory width on the memory board is encoded into the CSWIDTH[1:0] signals as shown in Table E-1. Table E-1 Memory width encoding CSWIDTH[1:0] Width 00 8 bit 01 16 bit 10 32 bit (default) 11 No memory present Note Additional configuration information is present in the E2PROM on the expansion board, see EEPROM contents on page E-6. E-4 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Memory Expansion Boards E.2 Fitting a memory board To install a memory expansion board: 1. Ensure that the PB926EJ-S is powered down. 2. Align the memory expansion board with the connectors on the PB926EJ-S as shown in Figure E-3. 3. Press the module into the connector. Figure E-3 Memory board installation locations ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Memory Expansion Boards E.3 EEPROM contents There are three serial devices on the PB926EJ-S serial bus: • Dynamic Memory Expansion EEPROM at 0xA0 for write, 0xA1 for read • Static Memory Expansion EEPROM at 0xA2 for write, 0xA3 for read • Real Time Clock (Time of Year) at 0xD0 for write, 0xD1 for read See Serial bus interface on page 4-86 for details on the serial bus interface.
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Memory Expansion Boards Table E-2 Chip Select information block Function Address offset Memory Type 0x0 0x0 = Reserved, 0x1 = Static NOR flash 2, 0x2 = Static NOR flash 1, 0x3 = Static SRAM, 0x4–0x80 = Reserved, 0x81 = Single Data Rate SDRAM, 0x82 = Sync Flash, 0x83–0xFE = Reserved, 0xFF = Not fitted. Memory Width 0x01 Bits [3:0] indicate the chip-select width: Value 0 = byte wide, 1 = 16-bit wide, 2 = 32-bit wide, 3 = Reserved.
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Memory Expansion Boards 0x00 EXPnCS DYCS1 0x30 CS4 DYCS2 0x60 CS5 DYCS3 CS6 Not used 0x90 0xC0 CS7 Not used Board string and CRC Board string and CRC 0xF0 Static chip select information block 0xFF Dynamic chip select information block Figure E-4 Chip select information block The contents of a typical static memory expansion EEPROM with devices on EXPnCS and CS4 is listed in Table E-3. Unused chip select blocks are filled with 0xFF.
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Memory Expansion Boards Table E-3 Example contents of a static memory expansion EEPROM (continued) Address offset Contents Contents 0x8–0xF Reserved 0xFF 0x10–0x2F EXPnCS memory device string "Intel GE28F256K3C120" + null character 0x30 CS4 memory type 0x01 = Static SRAM 0x31 CS4 memory width 0x02 - 32 bit wide 0x32 CS4 access time in 0.1ps (LSB) 0x26 - LSB (of 550 which 550 * 0.1ns = 55ns access time) 0x33 CS4 access time in 0.1ps (MSB) 0x02 - MSB (of 550 which 550 * 0.
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Memory Expansion Boards Table E-3 Example contents of a static memory expansion EEPROM (continued) Address offset Contents Contents 0x92 CS6 access time in 0.1ps (LSB) 0xFF 0x93 CS6 access time in 0.
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Memory Expansion Boards Table E-4 Example contents of a dynamic memory expansion EEPROM Address Contents Example contents 0x00 DYCS1 memory type 0x81 - Single Data Rate SDRAM 0x01 DYCS1 memory width 0x12 - 32 bit chip select width, 16-bit device memory width 0x02 DYCS1 access time in 0.1ps (LSB) 0x4B - LSB (of 75 which 75 * 0.1ns = 7.5ns access time) 0x03 DYCS1 access time in 0.
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Memory Expansion Boards Table E-4 Example contents of a dynamic memory expansion EEPROM (continued) E-12 Address Contents Example contents 0x65 DYCS3 memory size in bytes 0xFF 0x66 DYCS3 memory size in bytes 0xFF 0x67 DYCS3 memory size in bytes (MSB) 0xFF 0x68-0x6F Reserved 0xFF 0x70-0x8F DYCS3 memory device string 0xFF 0x90-0xEF Reserved 0xFF 0xF0-0xFE Board manufacturer string "ARM HBI0123A" 0xFF Checksum Byte The LSB of the sum of bytes 0x00 to 0xFE Copyright © 2003-2010 ARM
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Memory Expansion Boards E.4 Connector pinout This section describes the connectors present on the expansion memory boards. E.4.1 Expansion connector The static and dynamic memory expansion boards use 120-way Samtec connectors as shown in Figure E-5. The connector pinout for the dynamic memory board is shown in Table E-5 on page E-14. The connector pinout for the static memory board is shown in Table E-6 on page E-16.
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Memory Expansion Boards Table E-5 SDR, Single data rate dynamic memory connector signals E-14 Pin No. Signal Pin No.
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Memory Expansion Boards Table E-5 SDR, Single data rate dynamic memory connector signals (continued) Pin No. Signal Pin No. Signal 51 DATA[25] 52 Reserved, do not drive 53 DATA[26] 54 Reserved, do not drive 55 DATA[27] 56 Reserved, do not drive 57 DATA[28] 58 Reserved, do not drive 59 DATA[29] 60 Reserved, do not drive 61 DATA[30] 62 SBSCL, E2PROM serial interface clock (3.3V signal level) 63 DATA[31] 64 SBSDA, E2PROM serial interface data (3.
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Memory Expansion Boards Table E-5 SDR, Single data rate dynamic memory connector signals (continued) Pin No. Signal Pin No.
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Memory Expansion Boards Table E-6 Static memory connector signals (continued) Pin No. Signal Pin No.
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Memory Expansion Boards Table E-6 Static memory connector signals (continued) E-18 Pin No. Signal Pin No. Signal 63 DATA[31] 64 SBSDA, E2PROM serial interface data (3.3V signal level) 65 ADDR[0] 66 nRESET 67 ADDR[1] 68 nBOARDPOR, asserted on hardware power cycle 69 ADDR[2] 70 nFLWP, flash write protect. Drive HIGH to write to flash. 71 ADDR[3] 72 nEARLYRESET, Reset signal. Differs from nRESET in that it is not delayed by nWAIT.
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Memory Expansion Boards Table E-6 Static memory connector signals (continued) Pin No. Signal Pin No. Signal 95 ADDR[15] 96 nCS[0] 97 ADDR[16] 98 nBUSY, Indicates that memory is not ready to be released from reset. If LOW, this signal holds nRESET active.
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Memory Expansion Boards E.5 Mechanical layout Figure E-6 shows the dynamic memory expansion board (viewed from above). 42.00mm Pin 1 1.0mm 45.00mm 2mm Samtec QTH-060-02-F-D-A (40mm x 7.11mm) Figure E-6 Dynamic memory board layout Figure E-7 shows the static memory expansion board (viewed from above). 45.00mm 0.37mm 42.00mm Pin 1 2mm Samtec QSH-060-01-F-D-A (41.27mm x 7.1mm) Figure E-7 Static memory board layout E-20 Copyright © 2003-2010 ARM Limited. All rights reserved.
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Appendix F RealView Logic Tile This appendix describes the signals present on the RealView Logic Tile expansion headers and give the steps required to install a RealView Logic Tile on the PB926EJ-S. It contains the following sections: • About the RealView Logic Tile on page F-2 • Fitting a RealView Logic Tile on page F-3 • Header connectors on page F-4. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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RealView Logic Tile F.1 About the RealView Logic Tile The ARM RealView Logic Tiles, such as the LT-XC2V6000, enable developing AMBA AHB and APB peripherals, or custom logic, for use with ARM cores. Figure F-1 shows the RealView Logic Tile signals present on the PB926EJ-S connectors.
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RealView Logic Tile F.2 Fitting a RealView Logic Tile Figure F-2 shows a RealView Logic Tile mounted on the PB926EJ-S. Figure F-2 RealView Logic Tile fitted on PB926EJ-S ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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RealView Logic Tile F.3 Header connectors This section gives an overview of the RealView Logic Tile header connectors on the PB926EJ-S. For more detail, see the documentation for your RealView Logic Tile. There are three headers on the top and bottom of the tile. The HDRX and HDRY headers are 180-way and the HDRZ connectors are 300-way. Warning There is a limit to the number of RealView Logic Tiles which can be stacked on a RealView baseboard. For the PB926EJ-S the recommended limit is two.
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RealView Logic Tile Figure F-3 HDRX, HDRY, and HDRZ (upper) pin numbering F.3.1 JTAG The JTAG signals for the FPGA on the RealView Logic Tile are routed through the headers to the tile at the top of the stack and from there back down through the tile. There is not a JTAG connector on the RealView Logic Tile. Use the JTAG or USB debug connector on the PB926EJ-S.
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RealView Logic Tile Caution The RealView Logic Tile mounted on the PB926EJ-S must use the default 3.3V signal levels. F.3.3 RealView Logic Tile I/O The signals from the UART0, UART1, UART2, SSP, and SCI connectors to the ARM926EJ-S PXP Development Chip can be isolated by pulling the nDRVINENx signals HIGH. This enables logic in the RealView Logic Tile to safely drive the Development Chip signals without contention with external devices on the connectors (see Figure F-4).
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RealView Logic Tile F.3.4 RealView Logic Tile clocks The PB926EJ-S can receive the global clock or transmit the global clock to all of the boards in the RealView Logic Tile stack. Table F-1 on page F-8 lists the RealView Logic Tile clocks. Also, the clock multiplexor can select clock signals from the RealView Logic Tiles as the source for the M1, M2, and S clocks. The CLK_GLOBAL signal is present on all RealView Logic Tiles. The signal goes to the CLK_GLOBAL_INinput of the FPGAs on the tiles.
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RealView Logic Tile Ensure that your RealView Logic Tile configuration is compatible with the clock sources you are using on the PB926EJ-S. See RealView Logic Tile clocks on page 3-52 for more information on clock selection and routing. Table F-1 RealView Logic Tile clock signals PB926EJ-S signal RealView Logic Tile signal (top header) Direction Description GLOBALCLK CLK_GLOBAL I/O Global clock connected to all RealView Logic Tiles. Each tile and the PB926EJ-S can accept or generate the clock.
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RealView Logic Tile Table F-1 RealView Logic Tile clock signals (continued) PB926EJ-S signal RealView Logic Tile signal (top header) Direction Description HCLKM2L2F XU129 From tile RealView Logic Tile clock to multiplexor that provides M2 clock for the FPGA. HCLKSL2F XU130 From tile RealView Logic Tile clock to multiplexor that provides S clock for the FPGA. HCLKM1L2S XU131 From tile RealView Logic Tile clock to multiplexor that provides M1 clock for the development chip.
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RealView Logic Tile xCLKEXT external clocks for dev. chip peripherals GLOBALCLK XTALCLKDRV HCLKCTRL0 ARM 926EJ-S Dev.
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RealView Logic Tile F.3.5 AHB buses used by the FPGA and RealView Logic Tiles AHB M1, AHB M2, and AHB S buses are connected to both the FPGA and to the RealView Logic Tile stack. However, the user-implemented system in the tile must co-operate with the system implemented within the PB926EJ-S FPGA when using these buses: AHB M1 The AHB M1 bus can only be connected to AHB slaves in the Logic Tile stack. AHB M2 The AHB M2 bus can only be connected to AHB slaves in the Logic Tile stack.
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RealView Logic Tile multiplexing to combine with the PB926EJ-S slave outputs must be done with tristates in the RealView Logic Tile FPGA and PB926EJ-S FPGA. (This combination of multiplexing and tristates is identical to that used in Integrator Modules). It is recommended to use AHB M1 (not AHB M2) for expansion slaves in a RealView Logic Tile. The large address space will permit simpler decoding which will allow the bus to run faster.
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RealView Logic Tile S Slave Master Slave Master AHB M1 HLOCKM1 S S N/C 1 HGRANTM1 HREADYM1 HRESPM1 M1 Slaves HLOCKM2 HGRANTM2 HREADYM2 HRESPM2 N/C 1 1 1 Decoder AHB M2 M2 Default Slave M2 Decoder S nTILEDET 0 Logic Tile 1 00 1 0 1 0 1 PCI control LTBUSREQ M PCI interface S Master 1 Arbiter 0 FPGA BUSREQ S LTHGRANT GRANT ARM926EJ-S Dev.
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RealView Logic Tile F.3.6 Reset A user design in a RealView Logic Tile can reset the PB926EJ-S by driving the nSRST signal LOW. This has the same effect as pushing the reset button and forces the reset controller to the level specified by the SYS_RESETCTL register (see also, Reset Control Register, SYS_RESETCTL on page 4-31). nSRST is synchronized by the reset controller and can be driven from any clock source.
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Appendix G Configuring the USB Debug Connection When you install the RealView® ICE Micro Edition software that is provided with RVDS version 2.1 or higher, various features are added to the RealView® Debugger. This appendix explains how to use these additional features to configure the PB926EJ-S USB debug port connection, and how to connect RealView Debugger to the PB926EJ-S.
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Configuring the USB Debug Connection G.1 Installing the RealView ICE Micro Edition driver The first time you connect a USB cable between the USB debug port on the PB926EJ-S and your computer, the Windows operating system Plug and Play manager detects the unit and launches the Add New Hardware Wizard to install the RealView ICE Micro Edition driver. If the wizard does not appear, you can run it manually from the Control Panel. The installation process varies depending on the operating system you are using.
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Configuring the USB Debug Connection 4. G.1.3 Click Next. Specify where you want Windows to search for the driver files: a. Select Specify a location. b. Click the Browse... button and navigate to the installation directory you selected for the RVI-ME software in Installing the RealView Developer Suite on page G-2. c. Click OK. 5. Click Next. The Add New Hardware Wizard locates the driver. 6. Click Next. Windows installs the driver. 7. Click Finish to close the wizard.
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Configuring the USB Debug Connection G.1.4 Installing the RealView ICE Micro Edition driver on Windows XP Professional To install the RealView ICE Micro Edition driver on Windows XP Professional: G-4 1. Ensure that no RealView Debugger component is running. 2. Connect a USB cable between the USB debug port and your computer. The Add New Hardware Wizard is launched, and displays a welcome message. 3. Click Next.
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Configuring the USB Debug Connection G.2 Changes to RealView Debugger When you install the RealView ICE Micro Edition software, it adds the following capabilities to RealView Debugger: • New nodes in the Connection Control window: — an ARM-ARM-DIR target vehicle node at the top level lists the direct connection devices.
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Configuring the USB Debug Connection G.3 Using the USB debug port to connect RealView Debugger To connect to the PB926EJ-S using the USB debug port, you use the same RealView Debugger features that you use for any other target. For more information about connecting RealView Debugger to targets, refer to the RealView Debugger documentation suite. Note The USB debug port on the PB926EJ-S does not support simultaneous multiple-core debug (for example, multiple cores present in external RealView Logic Tiles).
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Configuring the USB Debug Connection 4. Click on VPB926EJ-S USB in the Connection Control window. If the debugger is able to connect to the PB926EJ-S, the Connection Control window displays the connection to the ARM926EJ-S PXP Development Chip as shown in Figure G-3. Figure G-3 ARM926EJ-S PXP Development Chip detected Note If the there is not a VPB926EJ-S USB entry in the Connection Control window, the RVI-ME software is not installed.
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Configuring the USB Debug Connection • If the PB926EJ-S is not detected, one of the errors shown in Figure G-5 or Figure G-6 is displayed. If you see one of these errors, ensure that the USB cable is properly attached. Figure G-5 Error shown when no devices are detected Figure G-6 Error shown when the USB debug port is not functioning 5. Right-click on VPB926EJ-S USB in the Connection Control window and select Connection Properties from the context menu that appears.
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Configuring the USB Debug Connection Note The default values for the connection do not typically require changing. 7. Close the Connection Properties window and return to the Code window in the RealView Debugger. You can now use the RealView Debugger to download programs to the PB926EJ-S and debug them. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Configuring the USB Debug Connection G.4 Using the Debug tab of the RealView Debugger Register pane When you install the RealView ICE Micro Edition software and connect to a PB926EJ-S, a Debug tab is added to the Register pane of the RealView Debugger Code window. This controls various internal debugger registers, many of which are specific to using the USB debug port.
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Configuring the USB Debug Connection G.4.1 Global Properties The Global Properties area of the Debug tab contains settings that control the behavior of the USB debug port when it resets the target hardware. (See Table G-1.
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Configuring the USB Debug Connection G.4.2 Device Properties The settings in the Device Properties area of the Debug tab of the RealView Debugger register pane control the device that you are connected to. (See Table G-2.
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Configuring the USB Debug Connection G.4.3 Semihosting Properties The settings in the Semihosting Properties area of the Debug tab in the RealView Debugger Register pane are the same as those used for other debug targets. For details of these settings, see the RealView Debugger User Guide. ARM DUI 0224I Copyright © 2003-2010 ARM Limited. All rights reserved.
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Index A AACI interface 4-42 specification 3-56 AHB asynchronous mode 3-43 bridges 3-10 expansion memory 4-14 matrix 3-11 memory map 3-12 monitor 3-16, 4-41 monitor signals A-38 RealView Logic Tile F-11 timing B-6 B Block diagram AACI 3-57 AHB Monitor 3-16 asynchronous mode 3-44 ARM DUI 0224I character LCD 3-59 CLCD board power C-9 CLCDC 3-61 clocks 3-35, 3-41 configuration 3-9 development chip 3-3 DMA 3-65 Ethernet 3-68 FPGA 3-17 FPGA configuration 3-18 GPIO 3-71 interrupt 3-72 JTAG 3-100 KMI 3-74 MCI 3
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Index CLCD adaptor connectors C-15 controller 3-61, 4-47 register 4-32, 4-34 Clocks architecture 3-35 changing 3-43 development chip 3-39 logic tile 3-52 multiplexor 3-54 peripheral 3-51, 3-54 programmable 3-48 RealView Logic Tile F-7 reset register 4-39 restrictions B-5 test register 4-40 Configuration boot memory 2-3 Boot Monitor 2-7 FPGA 3-18 interfaces 3-94 JTAG 2-8 logic 3-22 memory 4-9 memory board E-3 PCI 4-79 RECONFIG 3-9 registers 4-17, 4-25 reset 3-22, 3-32 runtime 3-10 switches 2-3, 3-7 touchscr
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Index TCM 1-4 timing B-7 MOVE coprocessor 4-69 MPMC controller 4-71 System controller 4-95 Timers 4-96 UART 4-97 Watchdog 4-101 Product revision status xviii R N Numerical conventions xxi P PCI configuration 4-79 configuring D-2 connectors D-10 controller 4-74 interface 3-79 JTAG D-9 limitations 4-83 register 4-31 registers 4-75 switches D-4 Peripheral timing B-7 Power CLCD 4-32, 4-34 CLCD adaptor board C-7 connecting 2-13 control 3-33 PCI D-2 Smart Card 3-82 PrimeCell AACI 3-56, 4-42 CLCDC 3-61, 4-43,
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Index serial bus 3-80 Smart Card 3-83, A-3 SSP A-2 test A-33 touchscreen C-12 Trace A-37 UART 3-89, A-5 USB 3-92, A-6 USB debug A-36 VGA A-13 XTALCLKDRV 3-52 Smart Card interface 3-81 Specification electrical B-2 mechanical B-9 SSMC interface 4-91 SSP interface 3-84, 4-89 Switches boot memory 2-3 Boot Monitor 2-7 configuration 3-7 GP pushbutton 3-87 PCI D-4 user 3-87 System contoller 4-95 U UART interface 3-88, 4-97 USB interface 3-92, 4-99 signals A-6 USB debug port 2-8 RealView Debugger G-6 signals A-36