User guide

Hardware Description
3-24 Copyright © 2003-2010 ARM Limited. All rights reserved. ARM DUI 0224I
3.3.2 Reset level
Table 3-3 lists the default levels of reset that results from external sources.
Figure 3-12 on page 3-25 shows the activity on the reset signals at different levels of
reset.
The level of reset that results from pressing the RESET pushbutton or generating a
software reset can be configured by the SYS_RESETCTL register (see also, Reset
Control Register, SYS_RESETCTL on page 4-31). The ability to configure the reset level
gives greater flexibility in designing applications, FPGA images, and Logic Tile IP.
Set SYS_RESETCTL[8] to generate a software reset.
The reset levels specified by SYS_RESETCTL[2:0] are:
•
b000 is reserved
•
b001 resets to level 1, CONFIGCLR
•
b010 resets to level 2, CONFIGINIT
•
b011 resets to level 3, DLLRESET (DLL located in FPGA)
•
b100 resets to level 4, PLLRESET (located in ARM926EJ-S PXP Development
Chip)
•
b101 resets to level 5, PORESET
•
b110 resets to level 6, DOCRESET
•
b111 is reserved.
Table 3-3 Reset sources and effects
External source
Reset
level
Hardware
nBOARDPOR
generated
FPGA reloaded
and Dev. Chip
configured with
default values
Dev. Chip
reconfigured
from
SYS_CFGDATA
registers
Reset
generated
for CPU,
memory and
peripherals
Power on 0 Yes Yes Yes Yes
FPGA CONFIG
pushbutton
1 No Yes Yes Yes
DEV CHIP RECONFIG
pushbutton
2No No Yes Yes
RESET pushbutton or
software reset
6No No No Yes