ARM Integrator/CM940T User Guide ARM DUI 0125A
ARM Integrator/CM940T User Guide © Copyright ARM Limited 1999. All rights reserved. Release information Change history Description Issue Change 8 September1999 A New document Proprietary notice ARM, the ARM Powered logo, Thumb and StrongARM are registered trademarks of ARM Limited. The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, ARM7TDMI, ARM7TDMI-S, ARM9TDMI, PrimeCell, and STRONG are trademarks of ARM Limited.
Electromagnetic conformity This section contains electromagnetic conformity (EMC) notices. Federal Communications Commission Notice NOTE: This equipment has been tested and found to comply with the limits for a class A digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment.
iv © Copyright ARM Limited 1999. All rights reserved.
Contents ARM Integrator/CM940T User Guide Electromagnetic conformity ............................................................................................iii Preface About this document .................................................................................................... viii Further reading............................................................................................................... x Feedback .........................................................................
3.5 3.6 3.7 3.8 Chapter 4 Programmer’s Reference 4.1 4.2 4.3 4.4 Appendix A HDRA ........................................................................................................... A-2 HDRB ........................................................................................................... A-4 Specifications B.1 B.2 B.3 vi Memory organization .................................................................................... 4-2 Exception vector mapping ...............................
Preface This preface introduces the ARM Integrator/CM940T core module and its reference documentation. It contains the following sections: • About this document on page viii • Further reading on page x • Feedback on page xi. ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
About this document This document describes how to set up and use the ARM Integrator/CM940T core module. Intended audience This document has been written for experienced hardware and software developers to aid the development of ARM-based products using the ARM Integrator/CM940T as part of a development system. Organization This document is organized into the following chapters: Chapter 1 Introduction Read this chapter for an introduction to the core module.
Typographical conventions The following typographical conventions are used in this document: bold Highlights ARM processor signal names within text, and interface elements such as menu names. May also be used for emphasis in descriptive lists where appropriate. italic Highlights special terminology, cross-references and citations. typewriter Denotes text that may be entered at the keyboard, such as commands, file names and program names, and source code.
Further reading This section lists related publications by ARM Limited and other companies that may provide additional information.
Feedback ARM Limited welcomes feedback both on the ARM Integrator/CM940T core module and on the documentation. Feedback on this document If you have any comments about this document, please send email to errata@arm.com giving: • the document title • the document number • the page number(s) to which your comments refer • an explanation of your comments. General suggestions for additions and improvements are also welcome.
xii © Copyright ARM Limited 1999. All rights reserved.
Chapter 1 Introduction This chapter introduces the ARM Integrator/CM940T core module. It contains the following sections: ARM DUI 0125A • About the ARM Integrator/CM940T core module on page 1-2 • ARM Integrator/CM940T overview on page 1-4 • Links and indicators on page 1-8 • Test points on page 1-10 • Precautions on page 1-11. © Copyright ARM Limited 1999. All rights reserved.
Introduction 1.1 About the ARM Integrator/CM940T core module The Integrator/CM940T core module provides you with the basis of a flexible development system which can be used in a number of different ways. With power and a simple connection to a Multi-ICE debugger, the core module provides a basic development system. By mounting the core module onto a motherboard, you can build a realistic emulation of the system being developed.
Introduction Core module/motherboard connectors HDRB Reset button DIMM socket SDRAM DIMM Multi-ICE connector Processor core Power connector Memory controller and system bus bridge (FPGA) Core module/motherboard connectors HDRA Figure 1-1 Integrator/CM940T layout ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
Introduction 1.2 ARM Integrator/CM940T overview The major components on the core module are as follows: • ARM940T microprocessor core • core module FPGA which implements: — SDRAM controller — system bus bridge — reset controller — interrupt controller — status, configuration, and interrupt registers. • volatile memory comprising: — up to 256MB of SDRAM (optional) via DIMM socket — 256KB SSRAM. • SSRAM controller • clock generator • system bus connectors • Multi-ICE debug connector. 1.2.
Introduction 1.2.2 Core module FPGA The FPGA provides system control functions for the core module, enabling it to operate as a standalone development system or attached to a motherboard. These functions are outlined in this section and described in detail in Chapter 3 Hardware Description. SDRAM controller The SDRAM controller is implemented within the FPGA. This provides support for Dual In-line Memory Modules (DIMMs) with a capacity of between 16 and 256MB. See SDRAM controller on page 3-6.
Introduction Status and configuration space The status and configuration space contains status and configuration registers for the core module. These provide the following information and control: • type of processor and whether it has a cache, MMU, or protection unit • the position of the core module in a multi-module stack • SDRAM size, address configuration, and CAS latency setup • core module oscillator setup • interrupt control for the processor debug communications channel.
Introduction 1.2.5 Multi-ICE connector The Multi-ICE connector enables JTAG hardware debugging equipment, such as Multi-ICE, to be connected to the core module. It is possible to both drive and sense the system-reset line (nSRST), and to drive JTAG reset (nTRST) to the core from the Multi-ICE connector. See Multi-ICE support on page 3-21. Note JTAG test equipment supplied by other vendors may also be used. ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
Introduction 1.3 Links and indicators CFGLED POWER FPGA OK MISC CONFIG The core module provides one link and four surface-mounted LEDs. These are illustrated in Figure 1-3. Figure 1-3 Links and indicators 1.3.1 CONFIG link The core module has only one link, marked CONFIG. This is left open during normal operation. It is only fitted when downloading new FPGA and PLD configuration information. 1-8 © Copyright ARM Limited 1999. All rights reserved.
Introduction 1.3.2 LED indicators The functions of the four surface-mounted LEDs are summarized in Table 1-1. Table 1-1 LED functional summary ARM DUI 0125A Name Color Function MISC Green This LED is controlled via the control register (see CM_CTRL (0x1000000C) on page 4-11). FPGA OK Green This LED illuminates when the FPGA has successfully loaded its configuration information following power-on. POWER Green This LED illuminates to indicate that a 3.3V supply is present.
Introduction 1.4 Test points The core module provides two ground and five signal test points as an aid to debug. These are illustrated in Figure 1-4. TP6 TP7 TP1 Voltage regulator TP3 TP5 TP4 TP2 Figure 1-4 Test points The functions of the test points are summarized in Table 1-2.
Introduction 1.5 Precautions This section contains safety information and advice on how to avoid damage to the core module. 1.5.1 Ensuring safety Warning To avoid a safety hazard, only Safety Extra Low Voltage (SELV) equipment should be connected to the JTAG interface. 1.5.2 Preventing damage The core module is intended for use within a laboratory or engineering development environment.
Introduction 1-12 © Copyright ARM Limited 1999. All rights reserved.
Chapter 2 Getting Started This chapter describes how to set up and prepare the ARM Integrator/CM940T core module for use. It contains the following sections: ARM DUI 0125A • Setting up a standalone ARM Integrator/CM940T on page 2-2 • Attaching the ARM Integrator/CM940T to a motherboard on page 2-5. © Copyright ARM Limited 1999. All rights reserved.
Getting Started 2.1 Setting up a standalone ARM Integrator/CM940T To set up the core module as a standalone development system: 2.1.1 1. Optionally, fit an SDRAM DIMM. 2. Supply power. 3. Connect Multi-ICE. Fitting an SDRAM DIMM You should fit the following type of SDRAM module: • PC66- or PC100-compliant 168pin DIMM • unbuffered • 16MB, 32MB, 64MB, 128MB or 256MB. To install an SDRAM DIMM: 1. Ensure that the core module is powered down. 2. Open the SDRAM retaining latches outwards. 3.
Getting Started 2.1.3 Supplying power 5V 3.3V GND GND 3V3 5V When using the core module as a standalone development system, you should connect a bench power supply with 3.3V and 5V outputs to the power connector, as illustrated in Figure 2-1. Figure 2-1 Power connector Note This power connection is not required when the core module is fitted to a motherboard. ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
Getting Started 2.1.4 Connecting Multi-ICE When you are using the core module as a standalone system, Multi-ICE debugging equipment can be used to download programs. The Multi-ICE setup for a standalone core module is shown in Figure 2-2. Multi-ICE server/debugger Parallel cable Multi ICE Multi-ICE unit Power supply Core module Figure 2-2 Multi-ICE connection to a core module Caution Because the core module does not provide non-volatile memory, programs are lost when the power is removed.
Getting Started 2.2 Attaching the ARM Integrator/CM940T to a motherboard Attach the core module onto a motherboard (for example, the ARM Integrator/SP) by engaging the connectors HDRA and HDRB on the bottom of the core module with the corresponding connectors on the top of the motherboard. The lower side of the core module has sockets and the upper side of the core module has plugs to allow core modules to be mounted on top of one another. A maximum of four core modules can be stacked on a motherboard.
Getting Started 2.2.1 Core module ID The ID of the core module is configured automatically by the connectors (there are no links to set) and depends on its position in the stack: • core module 0 is installed first • core module 1 is installed next, and cannot be fitted without core module 0 • core module 2 is installed next, and cannot be fitted without core module 1 • core module 3 is installed next, and cannot be fitted without core module 2.
Chapter 3 Hardware Description This chapter describes the on-board hardware. It contains the following sections: • ARM940T microprocessor core on page 3-2 • SSRAM controller on page 3-3 • Core module FPGA on page 3-4 • SDRAM controller on page 3-6 • Reset controller on page 3-8 • System bus bridge on page 3-11 • Clock generators on page 3-17 • Multi-ICE support on page 3-21. ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
Hardware Description 3.1 ARM940T microprocessor core The ARM940T cached processor macrocell is a member of the ARM9 Thumb family of high-performance 32-bit system-on-a-chip processors. It provides the following: • ARM9TDMI RISC integer CPU • 4KB instruction and data caches • write buffer • protection unit • AMBA ASB bus interface. The ARM940T processor employs a Harvard cache architecture, and so has separate 4KB instruction and 4KB data caches. Each cache has a 4-word line length.
Hardware Description 3.2 SSRAM controller The SSRAM controller is implemented in a Xilinx 9572 PLD which enables the SSRAM to achieve single-cycle operation. In addition to controlling accesses to the SSRAM, the controller generates the processor response signals (BWAIT, BERROR, BLAST) for all accesses to: • SSRAM • SDRAM • status and configuration register space • system bus bridge. ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
Hardware Description 3.3 Core module FPGA The core module FPGA contains five main functional blocks: • SDRAM controller on page 3-6 • Reset controller on page 3-8 • System bus bridge on page 3-11 • Core module registers on page 4-7 • Debug interrupt controller, see Debug communications interrupts on page 3-27. The FPGA provides sufficient functionality for the core module to operate as a standalone development system, although with limited capabilities.
Hardware Description At power-up the FPGA loads its configuration data from a flash memory device. Parallel data from the flash is serialized by the Programmable Logic Device (PLD) into the configuration inputs of the FPGA. Figure 3-2 shows the FPGA configuration mechanism.
Hardware Description 3.4 SDRAM controller The core module provides support for a single 16, 32, 64, 128, or 256MB SDRAM DIMM. 3.4.1 SDRAM operating mode The operating mode of the SDRAM devices is controlled with the mode set register within each SDRAM. These registers are set immediately after power-up to specify: • a burst size of four for both reads and writes • Column Address Strobe (CAS) latency of 2 cycles.
Hardware Description a 64 x 32-bit area of memory (CM_SPD) within the SDRAM controller. The SPD flag is set in the SDRAM control register (CM_SDRAM) when the SPD data is available. This copy can be randomly accessed at 0x10000100 to 0x100001FC (see CM_SPD (0x10000100 to 0x100001FC) on page 4-16). Write accesses to the SPD EEPROM are not supported. ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
Hardware Description 3.5 Reset controller The core module FPGA incorporates a reset controller which enables the core module to be reset as a standalone unit or as part of an Integrator development system. The core module can be reset from five sources: • reset button • motherboard • other core modules • Multi-ICE • software. Figure 3-3 shows the architecture of the reset controller.
Hardware Description 3.5.1 Reset signals Table 3-1 describes the external reset signals. Table 3-1 Reset signal descriptions Name Description Type Function BnRES_M Processor reset Output The BnRES_M signal is used to reset the processor core. It is generated from nSRST LOW when the core module is used standalone, or nSYSRST LOW when the core module is attached to a motherboard. It is asserted as soon as the appropriate input becomes active.
Hardware Description 3.5.2 Software resets The core module FPGA provides a software reset which can be triggered by writing to the reset bit in the CM_CTRL register. This generates the internal reset signal SWRST which generates nSRST and resets the whole system (see CM_CTRL (0x1000000C) on page 4-11). 3-10 © Copyright ARM Limited 1999. All rights reserved.
Hardware Description 3.6 System bus bridge The system bus bridge provides an asynchronous bus interface between the local system bus and system bus connecting the motherboard and other modules. Inter-module accesses are supported by two 16 x 74-bit FIFOs. Each of the 16 entries in the FIFOs contains: • 32-bit data used for write transfers • 32-bit address used for reads and writes • 10-bit transaction control used for reads and writes. 3.6.
Hardware Description Write transactions from the processor to the system bus normally complete on the local memory bus in a single cycle. The data, address, and control information associated with the transfer are posted into FIFO, and the transfer on the system bus occurs some time later when that bus is available. This means that system bus error responses to write transfers are not reported back to the processor as data aborts.
Hardware Description 3.6.2 Motherboard accesses to SDRAM The second FIFO supports read and write accesses by system bus masters on the motherboard and other core modules to the local core module memory. System bus writes The data routing for system bus writes to SDRAM is illustrated in Figure 3-6.
Hardware Description System bus reads The data routing for system bus reads from SDRAM is illustrated in Figure 3-7. Processor core SDRAM controller SDRAM FIFO FIFO Motherboard Figure 3-7 System bus reads from SDRAM For system bus reads, the address and control information also pass through the FIFO, but the returned data from the SDRAM bypasses the FIFO. The order of transactions on the system bus and the memory bus is preserved.
Hardware Description 3.6.4 System bus signal routing The core module is mounted onto a motherboard via the connectors HDRA and HDRB. As well as carrying all signal connections between the boards, these provide mechanical mounting (see Attaching the ARM Integrator/CM920T to a motherboard on page 2-5). HDRA The signals on the HDRA connectors are tracked between the socket on the underside and the plug on the top so that pin 1 connects to pin 1, pin 2 to pin 2 and so on.
Hardware Description The example in Figure 3-8 illustrates how a group of four signals (labelled A, B, C, and D) are routed through a group of four connector pins up through the stack. It highlights how signal C is rotated as it passes up through the stack and only utilized on module 2. All four signals are rotated and utilized in a similar way, as follows: • signal A on core module 0 • signal B on core module 1 • signal C used on core module 2 • signal D used on core module 3.
Hardware Description 3.7 Clock generators The core module provides its own clock generators and operates asynchronously with the motherboard. The clock generator provides two programmable clocks: • processor core clock CORECLK • processor local memory bus clocks LCLK and nLCLK. In addition, a fixed-frequency reference clock REFCLK is supplied to the FPGA. These clocks are supplied by two MicroClock ICS525 devices and by the SSRAM controller PLD, as illustrated in Figure 3-9.
Hardware Description 3.7.1 Processor core clock (CORECLK) The frequency of CORECLK is controllable in 1MHz steps in the range 12MHz to 160MHz. This is achieved by setting the Voltage Controlled Oscillator (VCO) divider and output divider for the CORECLK generator via the CM_OSC register. The VCO divider is controlled by the C_VDW bits and output divider is controlled by the C_OD bits. The reference divider value is fixed.
Hardware Description 3.7.2 Processor bus clocks (LCLK and nLCLK) The frequency of the processor bus clocks LCLK and nLCLK is determined by the frequency of 2XCLK. The clock signal 2XCLK is divided by 2 by the SSRAM controller PLD to produce LCLK and nLCLK. The frequency of LCLK is controllable in 0.5MHz steps in the range 6MHz to 66MHz. This is achieved by programming the VCO and output divider bits for the 2XCLK generator in the CM_OSC register.
Hardware Description The LCLK clock signal is buffered by a 5-output low-skew buffer PI49FCT3805 to drive five loads. These are: • SDRAM_CLK[3:0] • SSRAM_CLK. The nLCLK clock signal is a phase-aligned inversion of the LCLK signal. It is buffered by a 5-output low-skew buffer PI49FCT3805 to four loads. These are: • ARM_BCLK_M • PLD_BCLK_M • FPGA_BCLK_M • LA_BCLK_M. All clocks are series terminated with 33Ω resistors placed as close to the source as possible. 3.7.
Hardware Description 3.8 Multi-ICE support The core module provides support for debug using JTAG. It provides a Multi-ICE connector and JTAG scan paths around the development system. Figure 3-10 shows the Multi-ICE connector and the CONFIG link. Multi-ICE connector CONFIG link CFGLED Figure 3-10 JTAG connector, CONFIG link, and LED The CONFIG link is used to enable in-circuit programming of the FPGA and PLDs using Multi-ICE (see Debugging modes on page 3-23).
Hardware Description 3.8.1 JTAG scan path Core module Multi-ICE Figure 3-11 shows a simplified diagram of the scan path. TDO TDI TDI Processor core HDRB HDRB TDI TDO nMBDET Core module TDI Processor core HDRB HDRB Motherboard Figure 3-11 JTAG scan path (simplified) When the core module is used as a standalone development system, the JTAG scan path is routed through the processor core and back to the Multi-ICE connector.
Hardware Description 3.8.2 Debugging modes The core module is capable of operating in two modes: • normal debug mode • configuration mode. Normal debug mode During normal operation and software development, the core module operates in debug mode. The debug mode is selected by default (when a jumper is not fitted at the CONFIG link, see Figure 3-10 on page 3-21). In this mode, the processor core and debuggable devices on other modules are accessible on the scan chain, as shown in Figure 3-11 on page 3-22.
Hardware Description The configuration mode allows FPGA and PLD code to be updated as follows: 3.8.3 • The FPGAs are volatile, but load their configuration from flash memory. Flash memory, which itself does not have a JTAG port, can be programmed by loading designs into the FPGAs and PLDs which handle the transfer of data to the flash using JTAG. • The PLDs are non-volatile devices which can be programmed directly by JTAG.
Hardware Description Table 3-4 JTAG signal description Name Description Function DBGRQ Debug request (from JTAG equipment) DBGRQ is a request for the processor core to enter the debug state. It is provided for compatibility with third-party JTAG equipment. DBGACK Debug acknowledge (to JTAG equipment) DBGACK indicates to the debugger that the processor core has entered debug mode. It is provided for compatibility with third-party JTAG equipment.
Hardware Description Table 3-4 JTAG signal description (continued) Name Description Function RTCK Return TCK (to JTAG equipment) Some devices sample TCK (for example a synthesizable core with only one clock), and this has the effect of delaying the time at which a component actually captures data. RTCK is a mechanism for returning the sampled clock to the JTAG equipment, so that the clock is not advanced until the synchronizing device captured the data.
Hardware Description 3.8.4 Debug communications interrupts The ARM940T processor core incorporates EmbeddedICE hardware and provides a debug communications data register which is used to pass data between the processor and JTAG equipment. The processor accesses this register as a normal 32-bit read/write register and the JTAG equipment reads and writes the register using the scan chain. For a description of the debug communications channel, see the ARM940T Technical Reference Manual.
Hardware Description 3-28 © Copyright ARM Limited 1999. All rights reserved.
Chapter 4 Programmer’s Reference This chapter describes the memory map and the status and control registers. It contains the following sections: • Memory organization on page 4-2 • Exception vector mapping on page 4-6 • Core module registers on page 4-7 • Interrupt registers on page 4-19. ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
Programmer’s Reference 4.1 Memory organization This section describes the memory map. For a standalone core module, the memory map is limited to local SSRAM, SDRAM, and core module registers. For the full memory map of an Integrator development system, which includes a motherboard, you should refer to the user guide for the motherboard. 4.1.1 Core module memory map The core module has a fixed memory map which maintains compatibility with other ARM modules and Integrator systems.
Programmer’s Reference Motherboard detect The nMBDET signal operates as follows: nMBDET=0 The core module is attached to a motherboard, and accesses in the address range 0x0 to 0x3FFFF to the boot ROM or SSRAM are controlled by the REMAP bit. nMBDET=1 The core module is not attached, and accesses in the address range 0x0 to 0x3FFFF are routed to the SSRAM. Note The SSRAM is local, which means that it can only be read by the processor on the same core module.
Programmer’s Reference 4.1.3 SDRAM accesses The Integrator memory map provides a 256MB address space for SDRAM. When a smaller sized SDRAM DIMM is fitted, it is mapped repeatedly to fill the 256MB space. For example, a 64MB DIMM appears four times, as shown in Figure 4-2.
Programmer’s Reference System bus accesses to SDRAM If the core module is mounted on a motherboard, the SDRAM is mapped to appear at the aliased module memory region of the combined Integrator system bus memory map. The SDRAM can be accessed by all bus masters at its alias location, and accessed by the local processor at both its local and alias locations. The system bus address for a core module is automatically controlled by its position in the stack (see Core module ID on page 2-6).
Programmer’s Reference 4.2 Exception vector mapping The convention for ARM cores is to map the exception vectors to begin at address 0. However, the ARM940T core allows the vectors to be moved to 0xFFFF0000 by writing to the V bit in coprocessor 15 register 1 (CP15c1). The value of the V bit at reset is determined by the level on an external pin (VINITHI). To maintain compatibility across all cores, the default reset value maps the vector to begin at address 0 (see the ARM940T Technical Reference Manual).
Programmer’s Reference 4.3 Core module registers The core module status and control registers allow the processor to determine its environment and to control some core module operations. The registers, listed in Table 4-2, are located at 0x10000000 and can only be accessed by the local processor.
Programmer’s Reference 4.3.1 CM_ID (0x10000000) The core module ID register (CM_ID) is a read-only register that identifies the board manufacturer, board type, and revision. 31 24 23 MAN 16 15 ARCH 1211 FPGA 43 BUILD 0 REV Table 4-3 describes the core module ID register bits. Table 4-3 CM_ID register bit descriptions 4.3.
Programmer’s Reference 4.3.3 CM_OSC (0x10000008) The core module oscillator register (CM_OSC) is a read/write register that controls the frequency of the clocks generated by the two clock generators (see Clock generators on page 3-17). In addition, it provides information about processor bus mode setting. 31 25 24 Reserved 23 22 BMODE 12 11 10 20 19 L_OD L_VDW 8 7 R C_OD 0 C_VDW Before writing to the CM_OSC register, you must unlock it by writing the value 0x0000A05F to the CM_LOCK register.
Programmer’s Reference Table 4-4 CM_OSC register (continued) 4-10 Bits Name Access Function 11 Reserved Use read-modify-write to preserve value. 10:8 COREOD Read/write Core clock output divider: 000 = divide by 10 001 = divide by 2 (default) 010 = divide by 8 011 = divide by 4 100 = divide by 5 101 = divide by 7 110 = divide by 9 111 = divide by 6. 7:0 COREVCO Read/write Core clock VCO divider word. Defines the binary value of the V[7:0] pins of the clock generator (V[8] is tied low).
Programmer’s Reference 4.3.4 CM_CTRL (0x1000000C) The core module control register (CM_CTRL) is a read/write register that provides control of a number of user-configurable features of the core module. 31 4 Reserved 3 2 1 0 RESET REMAP nMBDET LED Table 4-5 describes the core module control register bits. Table 4-5 CM_CTL register ARM DUI 0125A Bits Name Access Function 31:8 Reserved Use read-modify-write to preserve value. 7:4 Reserved Use read-modify-write to preserve value.
Programmer’s Reference 4.3.5 CM_STAT (0x10000010) The core module status register (CM_STAT) is a read-only register that can be read to determine where in a multi-core module stack this core module is positioned. 31 8 7 Reserved 0 ID Table 4-6 describes the core module status register bits. Table 4-6 CM_STAT register 4-12 Bit Name Access Function 31:8 Reserved Use read-modify-write to preserve value.
Programmer’s Reference 4.3.6 CM_LOCK (0x10000014) The core module lock register (CM_LOCK) is a read/write register that is used to control access to the CM_OSC register, allowing it to be locked and unlocked. This mechanism prevents the CM_OSC register from being overwritten accidently. 31 17 Reserved 16 15 LOCKED 0 LOCKVAL Table 4-7 describes the core module lock register bits.
Programmer’s Reference 4.3.7 CM_SDRAM (0x10000020) The SDRAM status and control register (CM_SDRAM) is a read/write register used to set the configuration parameters for the SDRAM DIMM. This control is necessary because of the variety of module sizes and types available. Writing a value to this register automatically updates the mode register on the SDRAM DIMM.
Programmer’s Reference Table 4-8 CM_SDRAM register (continued) Bits Name Access Function 4:2 MEMSIZE Read/write These bits specify the size of the SDRAM module fitted to the core module. The bits are encoded as follows: 000 = 16MB 001 = 32MB 010 = 64MB (default) 011 = 128MB 100 = 256MB 101 = Reserved 110 = Reserved. 1:0 CASLAT Read/write These bits specify the CAS latency set for the core module. The bits are encoded as follows: 00 = Reserved 01 = Reserved 10 = 2 cycles (default) 11 = 3 cycles.
Programmer’s Reference 4.3.8 CM_SPD (0x10000100 to 0x100001FC) This area of memory contains a copy of the SPD data from the SPD EEPROM on the DIMM. Because accesses to the EEPROM are very slow, the data is copied to this memory during board initialization to allow faster random access to the SPD data (see Serial presence detect on page 3-6). The SPD memory contains 256 bytes of data, the most important of which are as shown in Table 4-9.
Programmer’s Reference Example 4-1 CM_BASE SPD_BASE EQU EQU 0x10000000 0x10000100 ; base address of Core Module registers ; base address of SPD information lightled LDR MOV STR ; turn on header r0, =CM_BASE ; r1,#5 ; r1,[r0,#0xc] ; ; setup SDRAM LED and remap memory load register base address set remap and led bits write the register readspdbit LDR AND CMP BNE ; check SPD bit is set r1,[r0,#0x20] ; read the status register r1,r1,#0x20 ; mask SPD bit (5) r1,#0x20 ; test if set readspdbit ; branch un
Programmer’s Reference not64 CMP BNE MOV B r5,#0x80 not128 r6,#0xe writesize ; is it 128MB? ; if no, move on ; store size and CAS latency of 2 not128 ; if it is none of these sizes then it is either 256MB, or ; there is no SDRAM fitted so default to 256MB.
Programmer’s Reference 4.4 Interrupt registers The core module provides a 3-bit IRQ controller and 3-bit FIQ controller to support the debug communications channel used for passing information between applications software and the debugger. The interrupt control registers are listed in Table 4-10.
Programmer’s Reference Enable set Set Enable Enable clear Clear Status Interrupt source Raw status nIRQ From other bit slices Figure 4-4 Interrupt control 4.4.1 CM_IRQ_STAT (0x10000040)/CM_FIQ_STAT (0x10000060) The status register contains the logical AND of the bits in the raw status register and the enable register. 4.4.2 CM_IRQ_RSTAT (0x10000044)/CM_FIQ_RSTAT (0x10000064) The raw status register indicates the signal levels on the interrupt request inputs.
Programmer’s Reference 4.4.4 CM_IRQ_ENCLR(0x1000004C)/CM_FIQ_ENCLR (0x1000006C) The clear set locations are used to set bits in the enable register as follows: • clear bits in the enable register by writing to the ENCLR location for the required IRQ or FIQ controller: 1 = CLEAR the bit. 0 = leave the bit unchanged. 4.4.5 Interrupt register bit assignment The bit assignments for the IRQ and FIQ status, raw status and enable register are shown in Table 4-11.
Programmer’s Reference 4.4.6 CM_SOFT_INTSET (0x10000050)/CM_SOFT_INTCLT (0x10000054) The core module interrupt controller provides a register for controlling and clearing software interrupts. This register is accessed using the software interrupt set and software interrupt clear locations. The set and clear locations are used as follows: • Set the software interrupt by writing to the CM_SOFT_INTSET location: 1 = SET the software interrupt 0 = leave the software interrupt unchanged.
Appendix A Signal Descriptions This index provides a summary of signals present on the core module main connectors. It contains the following sections: • HDRA on page A-2 • HDRB on page A-4. Note For the Multi-ICE connector pinout and signal descriptions see JTAG signals on page 3-24. ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
Signal Descriptions A.1 HDRA Figure A-1 shows the pin numbers of the HDRA plug and socket. All pins on the HDRA socket are connected to the corresponding pins on the HDRA plug.
Signal Descriptions The signals present on the pins labeled A[31:0], B[31:0], and C[31:0] are described in Table A-1. Table A-1 Bus bit assignment (for an AMBA ASB bus ) Pin label Name (ASB) Description A[31:0] System address bus System address bus B[31:0] Not used - C[31:0] System control bus See remainder of table.
Signal Descriptions A.2 HDRB The HDRB plug and socket have slightly different pinouts, as described below. A.2.1 HDRB socket pinout Figure A-2 shows the pin numbers of the socket HDRB on the underside of the core module, viewed from above the core module.
Signal Descriptions A.2.2 HDRB plug pinout Figure A-3 shows the pin numbers of the HDRB plug on the top of the core module.
Signal Descriptions A.2.3 Through-board signal connections The signals on the pins labeled E[31:0] are cross-connected between the plug and socket so that the signals are rotated through the stack in groups of four. For example, the first block of four are connected as shown in Table A-2.
Signal Descriptions A.2.4 HDRB signal descriptions Table A-3 describes the signals on the pins labeled E[31:0], F[31:0], and G[15:0].
Signal Descriptions Table A-3 HDRB signal description (continued) Pin label Name Description G4 TCK JTAG test clock G[3:1] MASTER[2:0] Master ID. Binary encoding of the master currently performing a transfer on the bus. Corresponds to the module ID and to the AREQ and AGNT line numbers. G0 nMBDET Motherboard detect pin Note Table A-3 shows signal descriptions for an AMBA ASB bus implementation. A-8 © Copyright ARM Limited 1999. All rights reserved.
Appendix B Specifications This appendix contains the specifications for the ARM Integrator/CM940T core module. It contains the following sections: • Electrical specification on page B-2 • Timing specification on page B-3 • Mechanical details on page B-4. ARM DUI 0125A © Copyright ARM Limited 1999. All rights reserved.
Specifications B.1 Electrical specification Table B-1 shows the core module electrical characteristics for the system bus interface. The core module uses 3.3V and 5V source. The 12V inputs are supplied by the motherboard but not used by the core module. Table B-1 Core module electrical characteristics B-2 Symbol Description Min Max Unit 3V3 Supply voltage (interface signals) 3.1 3.5 V 5V Supply voltage 4.75 5.25 V VIH High-level input voltage 2.0 3.
Specifications B.2 Timing specification Table B-2 provides the operating timing characteristics for the system bus interface signals. Table B-2 Core module timing (preliminary) Symbol Description Min Max Units FMAX Operating frequency - 25 MHz TCH Clock HIGH 19 - ns TCL Clock LOW 19 - ns TCO Clock to output – signals generated and sampled on same clock edge - 16.0 ns Clock to output – signals generated and sampled on different clock edge - 8.
Specifications B.3 Mechanical details The core module is designed to be stackable on a number of different motherboards. Its size allows it to be mounted onto a CompactPCI motherboard while allowing the motherboard to be installed in a card cage. Figure B-1 shows the mechanical outline of the core module. 148.0 10.0 128.0 10.0 Detail A HDRA HDRB 81.0 130-way connector (4 col x 30 row) Plug on top and socket on underside 100.
Index The items in this index are listed in alphabetic order, with symbols and numerics appearing at the end. The references given are to page numbers.
Index Connectors HDRA and HDRB 1-3 Multi-ICE 2-4 power 2-3 Controller clock 1-6, 3-17 reset 1-5, 3-8 SDRAM 1-5, 3-6 SSRAM 3-3 Controllers FIQ 4-19 IRQ 4-19 Core module control register 4-11 Core module FPGA 1-5 Core module ID 2-6 Core module registers 4-7 Core module, stack position 4-12 CORECLK 3-17, 3-18 D ii E F FCC notice iii FIFOs 3-11 FIQ controller 4-19 Fitting SDRAM 2-2 FPGA 1-5 G LCLK 3-17, 3-19 Local SDRAM 4-4 Location of connectors Lock register 4-13 1-3 HDRA 3-15 HDRA and HDRB connector
Index SDRAM operating mode 3-6 SDRAM repeat mapping 4-4 SDRAM status and control register 4-14 SDRAM, SPD memory 4-16 Serial presence detect 3-6 Setting CAS latency 4-15 Setting SDRAM size 4-15 Setup power connections 2-3 standalone 2-2 Software interrupt registers 4-22 Software reset 4-11 SPD memory 4-16 SPDOK bit 4-14 SSRAM accesses 4-2 SSRAM controller 3-3 Standalone core module 2-2 Status and configuration registers 1-6 Status register 4-12 Status register, interrupt 4-20 Supplying power 2-3 System arc
Index Index-iv © Copyright ARM Limited 1999. All rights reserved.
