Date of Issue: 12-Nov-2008 Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 ARM Core Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) Errata Notice This document contains the errata known at the date of issue covering supported releases from r1p1 up to and including revision r2p0 of Cortex-M3 (AT420) and Cortex-M3 with ETM (AT425) products. PR326-PRDC-009450 v2.0 © Copyright ARM Limited 2008. All rights reserved.
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Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Date of Issue: 12-Nov-2008 Introduction Scope This document describes errata categorised by level of severity.
Date of Issue: 12-Nov-2008 PR326-PRDC-009450 v2.0 Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 © Copyright ARM Limited 2008. All rights reserved.
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Date of Issue: 12-Nov-2008 Errata Summary Table The errata associated with this product affect product versions as below. A cell shown thus X indicates that the defect affects the revision shown at the top of that column.
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Date of Issue: 12-Nov-2008 Errata present on release r2p0-00rel0 563915: Event Register is not set by interrupts and debug Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0,r2p0-00rel0, Open. Description The event register used for WFE wake-up events should be set for the following conditions: 1.
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Date of Issue: 12-Nov-2008 602117: LDRD with base in list may result in incorrect base register when interrupted or faulted Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0,r2p0-00rel0, Open.
Date of Issue: 12-Nov-2008 Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Implications The base register will not be restored as expected preventing the instruction from being restarted correctly upon return from the interrupt service routine or from the fault handler. Workaround There are two workarounds for this erratum. However, if the instructions are always executed from the code space and faults cannot occur then a workaround is not required.
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Date of Issue: 12-Nov-2008 Errata fixed on release r2p0-00rel0 531064: SWJ-DP missing POR reset sync Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Impl, Present in: r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description In Cortex-M3 r0p0 and r1p0, the SWJ-DP has an internal reset synchronizer for the power on reset signal.
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Date of Issue: 12-Nov-2008 511864: Cortex-M3 may fetch instructions using incorrect privilege on return from an exception Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Date of Issue: 12-Nov-2008 532314: DWT CPI counter increments during sleep Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description The DWT contains a number of counters for the profiling of applications.
Date of Issue: 12-Nov-2008 Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 538714: Cortex-M3 TPIU Clock Domain crossing Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description Combinatorial paths exist in control signals crossing the asynchronous clock boundary between FCLK and TRACECLKIN.
Date of Issue: 12-Nov-2008 Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 548721: Internal write buffer could be active whilst asleep Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.
Date of Issue: 12-Nov-2008 463763: Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 BKPT in debug monitor mode can cause DFSR mismatch Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.
Date of Issue: 12-Nov-2008 Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 463764: Core may freeze for SLEEPONEXIT single instruction ISR Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0. Description The SLEEPONEXIT functionality causes the core to enter the sleep mode when the exit from the sole active interrupt occurs.
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Date of Issue: 12-Nov-2008 463769: Unaligned MPU fault during a write may cause the wrong data to be written to a successful first access Status Affects: product Cortex-M3, Cortex-M3 with ETM. Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.
Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 Date of Issue: 12-Nov-2008 Errata fixed on release r1p1-01rel0 429964: Async not generated if no trace in previous session Status Affects: product Cortex-M3 with ETM. Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0, Fixed in r1p1-01rel0.
Date of Issue: 12-Nov-2008 Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) ARM Errata Notice Document Revision 2.0 429965: Trigger packets sometimes not inserted in trace stream Status Affects: product Cortex-M3 with ETM. Fault status: Cat 2, Present in: r0p0,r1p0,r1p1,r1p1-00rel0, Fixed in r1p1-01rel0. Description It is possible to configure a trigger event for the ETM which is used to assist with trace capture and the subsequent analysis of trace by the user.
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