Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)

Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0

PR326-PRDC-009450 v2.0

Non Confidential

Implications

The base register will not be restored as expected preventing the instruction from being restarted correctly upon

return from the interrupt service routine or from the fault handler.

Workaround

There are two workarounds for this erratum. However, if the instructions are always executed from the code

space and faults cannot occur then a workaround is not required.

The first workaround is to replace the LDRD instruction affected by this erratum with other suitable instructions.

LDRD Ra, Rb, [Ra, #imm]

may be directly replaced by two LDR instructions which will produce exactly the same functionality:

LDR Rb, [Ra, #imm + 4]

LDR Ra, [Ra, #imm]

Alternatively, an LDRD with base in list may still be used if the base register is the second register in the list:

LDRD Rb, Ra, [Ra, #imm]

However, in order to achieve the same functionality this requires that the data at the two addresses are

swapped, or that the following instructions using Ra or Rb swap their source registers.

The second workaround can be applied when using Cortex-M3 r2p0. It is possible to prevent this erratum

occurring for the interrupt case by setting DISMCYCINT (bit[0]) in the Auxiliary Control Register which is located

at address 0xE000E008. This bit prevents the interruption of multi-cycle instructions and will therefore increase

the interrupt latency of Cortex-M3.

Setting DISMCYCINT does not prevent the second load being faulted which means that the base will still be

incorrect for bus faults or MPU faults.

Due to the performance impact of workaround two, and because workaround two does not address the fault

conditions of this erratum, ARM recommends that workaround one is used.