Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)
Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0
PR326-PRDC-009450 v2.0
© Copyright ARM Limited 2008. All rights reserved. Page 11 of 20
Non Confidential
Errata fixed on release r2p0-00rel0
531064: SWJ-DP missing POR reset sync
Status
Affects: product Cortex-M3, Cortex-M3 with ETM.
Fault status: Impl, Present in: r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.
Description
In Cortex-M3 r0p0 and r1p0, the SWJ-DP has an internal reset synchronizer for the power on reset signal.
Version r1p1 was upgraded to a newer version of SWJ-DP and this SWJ-DP did not have the same reset
synchronizer inside. As a result of that the timing of the power on reset could potentially be a problem.
Implications
none
Workaround
The r1p1 CortexM3Integration level can be modified to add the reset synchronizer.
The signal which has the problem is the nPOTRST input on SWJ-DP. Add a few new signals:
reg nPOTRSTQ; // DFF #1
reg nPOTRSTQQ; // DFF #2
wire inPOTRST; // reset bypass MUX
// Add the synchroniser DFFs:
always @ (posedge SWCLKTCK or negedge PORESETn) // nPOTRST synchroniser
if (!PORESETn) begin
nPOTRSTQ <= 1'b0;
nPOTRSTQQ <= 1'b0;
end
else begin
nPOTRSTQ <= 1'b1;
nPOTRSTQQ <= nPOTRSTQ;
end
// And a reset bypass MUX:
assign inPOTRST = RSTBYPASS ? PORESETn : nPOTRSTQQ;
// And connect the MUX output inPOTRST to the nPOTRST input of SWJ-DP:
DAPSWJDP uDAPSWJDP
(// Inputs
.nPOTRST (inPOTRST),