Specifications

Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)

Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0

PR326-PRDC-009450 v2.0

Non Confidential

463769: Unaligned MPU fault during a write may cause the wrong data to be written

to a successful first access

Status

Affects: product Cortex-M3, Cortex-M3 with ETM.

Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.

Description

When an unaligned store is executed by Cortex-M3 the transaction is split up into either two or three aligned

transactions forming constituent parts of the larger transaction. The MPU will check that these transactions are

permitted and will block them if necessary. If an unaligned transaction occurs where it overlaps two MPU

regions then each region relating to the part of the transaction that hits that region will be checked.

If an unaligned store occurs that crosses an MPU region boundary and has an MPU permission fault for the

second region check but not for the first region then it is possible for the second component’s data to be written

for the first successful transaction in place of the first transaction’s data. This can occur for writes to either the

D-Code or system bus but will only occur if one or more wait-states are applied for the first component of the

store.

Conditions

1. The full MPU is present and enabled with at least one region programmed and enabled.

2. An unaligned store is executed by the processor. The store can be to either the D-Code or the System

bus.

3. The store crosses an MPU region boundary.

4. The first region lookup passes, the second region lookup fails.

5. One or more wait states are applied via HREADYS or HREADYD.

Implications

The wrong data will be stored to a permitted address. However, a MemManage fault will occur immediately

pointing to the instruction that caused the fault. This may lead to the instruction being re-executed and the store

occurring successfully if it is for non-device memory. This would mean that the previously stored data would be

overwritten and the wrong value would never be seen. This may not be true for a shared memory system.

Workaround

A workaround is only required if the MPU is present and enabled. Either:

1. do not allow accesses to span more than one region or

2. do not allow unaligned accesses at all or

3. program the MPU correctly if applicable